2–21

2.9.4

Logical Interrupt Connection Diagram (INT0)

Figure 2–5 represents the logical connection of the interrupt sources and its relation with XINTO#. The priority

encoder generates an 8-bit vector, corresponding to 64 interrupt sources (not all are used). The interrupt priorities

are hard wired. Vector 4E is the highest and 00 is the lowest.

Interrupts

EX0

Priority

Encoder

Vector

Figure 2–5. Internal Vector Interrupt (EX0)

2.9.5

P2[7:0] Interrupt (INT1)

Figure 2–6 illustrates the conceptual Port-2 interrupt. All Port-2 input signals are connected in a logical OR to generate

INT1 interrupt. Note that the inputs are active low and INT1 is programed as an edge-triggered interrupt. In addition,

INT1 is connected to the suspend/resume logic for remote wake-up support. As illustrated, XINT-bit in MCU

configuration register (MCNFG) is used to select the EXI interrupt source. When XINT = 0, P3.3 is the source, and

when XINT = 1, P2[7:0] is the source.

Suspend/

Resume

Logic

P2[7:0]

P3.3

EX1

(INT1)

XINT-Bit

1

Figure 2–6. P2[7:0] Input Port Interrupt Generation