Functional Description

Data can be entered into the latch when both of the enable

inputs are LOW As long as this logic condition exists the

output of the latch will follow the input If either of the enable

inputs goes HIGH the data present in the latch at that time

is held in the latch and is no longer affected by data input

The master reset overrides all other input conditions and

forces the outputs of all the latches LOW when a LOW sig-

nal is applied to the Master Reset input

Truth Table

MR

E0E1

D

Qn

Operation

H

L

L

L

L

Data Entry

H

L

L

H

H

Data Entry

HL

H

X

Hold

HH

L

X

Hold

HH

H

X

Hold

L

X

X

X

L

Reset

Logic Diagram

TLF10208 – 3

9308

Symbol

Parameter

Units

Min

Max

Propagation Delay

30

ns

EntoQn

22

Propagation Delay

15

ns

Dn to Qn

18

Propagation Delay

22

ns

MR to Qn

3