LP38853

SNVS335E – DECEMBER 2006 – REVISED NOVEMBER 2015

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Table 1. Suggested Resistor Values

R1

R2

0.8 V

1.07 k

Ω

1.78 k

Ω

12 nF

12.4 kHz

0.9 V

1.50 k

Ω

1.87 k

Ω

8.2 nF

12.9 kHz

1 V

1.00 k

Ω

1.00 k

Ω

12 nF

13.3 kHz

1.1 V

1.65 k

Ω

1.37 k

Ω

8.2 nF

11.8 kHz

1.2 V

1.40 k

Ω

1.00 k

Ω

10 nF

11.4 kHz

1.3 V

1.15 k

Ω

715

Ω

12 nF

11.5 kHz

1.4 V

1.07 k

Ω

590

Ω

12 nF

12.4 kHz

1.5 V

2.00 k

Ω

1.00 k

Ω

6.8 nF

11.7 kHz

1.6 V

1.65 k

Ω

750

Ω

8.2 nF

11.8 kHz

1.7 V

2.55 k

Ω

1.07 k

Ω

5.6 nF

11.1 kHz

1.8 V

2.94 k

Ω

1.13 k

Ω

4.7 nF

11.5 kHz

Refer to the TI Application Note AN-1378 Method for Calculating Output Voltage Tolerances in Adjustable

7.3.6 Enable (EN) Operation

The EN pin provides a mechanism to enable, or disable, the regulator output stage. The EN pin has an internal

pullup, through a typical 180-k

function is not needed.

7.4 Device Functional Modes

7.4.1 Input Voltage

accuracy may be affected.

7.4.2 Bias Voltage

ensure proper operation of the device.

7.4.3 Enable Operation

100 mV of hysteresis built into the enable threshold provide noise immunity.

left open, stray capacitance on this pin must be minimized; otherwise, the output turnon is delayed while the

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