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PI6LC48C21 データシート(PDF) 4 Page - Pericom Semiconductor Corporation |
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PI6LC48C21 データシート(HTML) 4 Page - Pericom Semiconductor Corporation |
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4 / 6 page  4 www.pericom.com PI6LC48C21 Rev. B 08/04/15 PI6LC48C21 Single Output LVCMOS Clock Generator LVCMOS Test Circuit Power Supply Filtering Techniques As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor- mance, power supply isolation is required. The PI6LC48C21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.1μF bypass capacitors should be used for each pin. Figure below illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10μF bypass capacitor be connected to the VDDA pin. Phase Noise Plot 125MHz 15-0105 |
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