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2015-12-0001

PT0280-8

12/11/15

32

PT7C43390/43390C

Real-time Clock Module

 Free register access

*1. Set NO_ACK = 1 when reading.

Free Register Access

12. Reset After Communication Interruption

In case of communication interruption in the PT7C43390, for example, during communication the power supply voltage drops so

that only the master device is reset; the PT7C43390 does not operate the next procedure because the internal circuit keeps the state

prior to communication interruption. The PT7C43390 does not have a reset pin so that users usually reset its internal circuit by

inputting a stop condition. If the SDA is outputting "L" (during output of acknowledgment signal or reading), the PT7C43390

does not accept a stop condition from the master device. In this case, users are necessary to finish acknowledgment output or

reading of the SDA. Below Figure shows how to reset. First, input a start condition from the master device (the PT7C43390

cannot detect a start condition because the SDA in the PT7C43390 is outputting "L"). Next, input a clock pulse equivalent to 7-

byte data access (63-clock) from the SCL. During this, release the SDA line for the master device. By this procedure, SDA I/O

before communication interruption is finished, so that the SDA line in the PT7C43390 is released. After that, inputting a stop

condition resets the internal circuit so that restore the regular communication. This reset procedure is recommended to perform at

initialization of the system after rising the master device’s power supply voltage.

Figure How to Reset