ADC10731 datasheet(21/27 Pages) NSC

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Applications Hints (Continued)

3.0 APPLICATIONS INFORMATION

3.1 Multiplexer Configuration

The design of these converters utilizes a sampled-data com-

parator structure, which allows a differential analog input to

be converted by the successive approximation routine.

The actual voltage converted is always the difference be-

tween an assigned “+” input terminal and a “−” input terminal.

The polarity of each input terminal or pair of input terminals

being converted indicates which line the converter expects

to be the most positive.

A unique input multiplexing scheme has been utilized to pro-

vide multiple analog channels. The input channels can be

software

configured

into

three

modes:

differential,

single-ended, or pseudo-differential.

Figure 13 illustrates the

three modes using the 4-channel MUX of the ADC10734.

The eight inputs of the ADC10738 can also be configured in

any of the three modes. The single-ended mode has

CH0–CH3 assigned as the positive input with COM serving

as the negative input. In the differential mode, the

ADC10734 channel inputs are grouped in pairs, CH0 with

CH1 and CH2 with CH3. The polarity assignment of each

channel in the pair is interchangeable. Finally, in the

pseudo-differential mode CH0–CH3 are positive inputs re-

ferred to COM which is now a pseudo-ground. This

pseudo-ground input can be set to any potential within the in-

put common-mode range of the converter. The analog signal

conditioning required in transducer-based data acquisition

systems is significantly simplified with this type of input flex-

ibility.

One

converter

package

can

now

handle

ground-referred inputs and true differential inputs as well as

signals referred to a specific voltage.

The analog input voltages for each channel can range from

50 mV below GND to 50 mV above V

+ = DV+ = AV+ without

degrading conversion accuracy. If the voltage on an unse-

lected channel exceeds these limits it may corrupt the read-

ing of the selected channel.

3.2 Reference Considerations

The voltage difference between the V

REF

+ and V

REF

− inputs

defines the analog input voltage span (the difference be-

tween V

IN(Max) and VIN(Min)) over which 1023 positive and

1024 negative possible output codes apply.

The value of the voltage on the V

REF

+ or V

REF

− inputs can be

anywhere between AV

+ + 50 mV and −50 mV, so long as

REF

+ is greater than V

REF

−. The ADC10731/2/4/8 can be

used in either ratiometric applications or in systems requiring

absolute accuracy. The reference pins must be connected to

a voltage source capable of driving the minimum reference

input resistance of 5 k

Ω.

The internal 2.5V bandgap reference in the ADC10731/2/4/8

is available as an output on the VREFOut pin. To ensure op-

timum performance this output needs to be bypassed to

ground with 100 µF aluminum electrolytic or tantalum ca-

pacitor. The reference output can be unstable with capacitive

loads greater than 100 pF and less than 100 µF. Any capaci-

tive loading less than 100 pF and greater than 100 µF will not

cause oscillation. Lower output noise can be obtained by in-

creasing the output capacitance. A 100 µF capacitor will yield

a typical noise floor of

The pseudo-differential and differential multiplexer modes al-

low for more flexibility in the analog input voltage range since

the “zero” reference voltage is set by the actual voltage ap-

plied to the assigned negative input pin.

In a ratiometric system (

Figure 14), the analog input voltage

is proportional to the voltage used for the A/D reference. This

voltage may also be the system power supply, so V

REF+ can

also be tied to AV

+. This technique relaxes the stability re-

quirements of the system reference as the analog input and

A/D reference move together maintaining the same output

code for a given input condition.

For absolute accuracy (

Figure 15), where the analog input

varies between very specific voltage limits, the reference pin

can be biased with a time- and temperature-stable voltage

source that has excellent initial accuracy. The LM4040,

LM4041 and LM185 references are suitable for use with the

ADC10731/2/4/8.

The minimum value of V

REF (VREF = VREF+– VREF−) can be

quite small (see Typical Performance Characteristics) to al-

low direct conversion of transducer outputs providing less

than a 5V output span. Particular care must be taken with re-

gard to noise pickup, circuit layout and system error voltage

sources when operating with a reduced span due to the in-

creased sensitivity of the converter (1 LSB equals V

REF/

1024).

3.3 The Analog Inputs

Due to the sampling nature of the analog inputs, at the clock

edges short duration spikes of current will be seen on the se-

lected assigned negative input. Input bypass capacitors

should not be used if the source resistance is greater than

Ω since they will average the AC current and cause an ef-

fective DC current to flow through the analog input source re-

sistance. An op amp RC active lowpass filter can provide

both impedance buffering and noise filtering should a high

impedance signal source be required. Bypass capacitors

may be used when the source impedance is very low without

any degradation in performance.

In a true differential input stage, a signal that is common to

both “+” and “−” inputs is canceled. For the ADC10731/2/4/8,

the positive input of a selected channel pair is only sampled

once before the start of a conversion during the acquisition

time (t

A). The negative input needs to be stable during the

complete conversion sequence because it is sampled before

each decision in the SAR sequence. Therefore, any AC

common-mode signal present on the analog inputs will not

be completely canceled and will cause some conversion er-

rors. For a sinusoid common-mode signal this error is:

ERROR(max) = VPEAK (2 π fCM)(tC)

where f

CM is the frequency of the common-mode signal,

PEAK is its peak voltage value, and tC is the A/D’s conver-

sion time (t

= 12/f

CLK).

For example, for a 60 Hz

common-mode signal to generate a 1⁄4 LSB error (0.61 mV)

with a 4.8 µs conversion time, its peak value would have to

be approximately 337 mV.

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