ADC12L038 Hardware Power Up/Down

DS011830-32

Note: Hardware power up/down may occur at any time. If PD is high while a conversion is in progress that conversion will be corrupted and erroneous data will

be stored in the output shift register.

ADC12L038 Configuration Modification — Example of a Status Read

DS011830-33

Note: In order for all 9 bits of status information to be accessible the last conversion programmed before Cycle N needs to have a resolution of 8 bits plus sign,

12 bits, 12 bits plus sign, or greater.

DS011830-34

FIGURE 5. Protecting the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 Analog Pins

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