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AD7989-5BCPZ-R2 データシート(PDF) 5 Page - Analog Devices

部品番号 AD7989-5BCPZ-R2
部品情報  18-Bit, 100 kSPS/500 kSPS PulSAR ADCs in MSOP/LFCSP
PDF  24 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD7989-5BCPZ-R2 データシート(HTML) 5 Page - Analog Devices

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Data Sheet
AD7989-1/AD7989-5
TIMING SPECIFICATIONS
TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted. See Figure 2 and Figure 3 for load conditions.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
AD7989-1
Throughput Rate
100
kSPS
Conversion Time: CNV Rising Edge to Data Available
tCONV
9500
ns
Acquisition Time
tACQ
500
ns
Time Between Conversions
tCYC
10
µs
AD7989-5
Throughput Rate
500
kSPS
Conversion Time: CNV Rising Edge to Data Available
tCONV
1600
ns
Acquisition Time
tACQ
400
ns
Time Between Conversions
tCYC
2
μs
CNV Pulse Width (CS Mode)
tCNVH
500
ns
SCK Period (CS Mode)
tSCK
VIO Above 4.5 V
10.5
ns
VIO Above 3 V
12
ns
VIO Above 2.7 V
13
ns
VIO Above 2.3 V
15
ns
SCK Period (Chain Mode)
tSCK
VIO Above 4.5 V
11.5
ns
VIO Above 3 V
13
ns
VIO Above 2.7 V
14
ns
VIO Above 2.3 V
16
ns
SCK Low Time
tSCKL
4.5
ns
SCK High Time
tSCKH
4.5
ns
SCK Falling Edge to Data Remains Valid
tHSDO
3
ns
SCK Falling Edge to Data Valid Delay
tDSDO
VIO Above 4.5 V
9.5
ns
VIO Above 3 V
11
ns
VIO Above 2.7 V
12
ns
VIO Above 2.3 V
14
ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
tEN
VIO Above 3 V
10
ns
VIO Above 2.3V
15
ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
tDIS
20
ns
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
tSSDICNV
5
ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
tHSDICNV
2
ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
tSSCKCNV
5
ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
tHSCKCNV
5
ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
tSSDISCK
2
ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
tHSDISCK
3
ns
Rev. A | Page 5 of 24



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