when driving 10K ECL. Noise margins will not be affected

when interfacing to F100K since F100K is fully voltage and

temperature compensated.

OUTPUT RISE AND FALL TIMES

Output load capacitance can significantly affect output rise

and fall times. The effect of load capacitance, stray or other-

wise, may be reduced by placing the output back-match re-

sistor close to the output pin and by minimizing all intercon-

necting trace lengths.

Figure 8 shows the effect on risetime

of parallel load capacitance across a 150

Ω load.

DS100085-9

FIGURE 6. Output Stage

DS100085-10

FIGURE 7. Differential Input DC Coupled Output

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