Figure 1

Enable/Disable Operation Using +5V Supplies

The CLC407 has a TTL & CMOS logic compatible

disable function. Apply a logic low (i.e. < 0.8V) to pin

8, and the CLC407 is guaranteed disabled across its

temperature range. Apply a logic high to pin 8, (i.e. >

2.0V) and the CLC407 is guaranteed enabled. Voltage,

not current, at pin 8 determines the enable/disable

state of the CLC407.

Disable the CLC407 and its inputs and output become

high impedances. While disabled, the CLC407’s quies-

cent power drops to 8mW.

Use the CLC407’s disable to create analog switches or

multiplexers. Implement a single analog switch with

one CLC407 positioned between an input and output.

Create an analog multiplexer with several CLC407s.

Tie the outputs together and put a different signal on

each CLC407 input.

Operate the CLC407 without connecting pin 8.

An

internal 20k

Ω pull-up resistor guarantees the CLC407

is enabled when pin 8 is floating.

Enable/Disable Operation for Single or

Unbalanced Supply Operation

Figure 2

Figure

2

illustrates

the

internal

enable/disable

operation of the CLC407. When pin 8 is left floating or

the CLC407 circuitry. When pin 8 is less than 0.8V

flowing in the bias circuitry. The CLC407 is now disabled.

Disable Limitations

inverting gain configurations.

Do not apply voltages

Input - Bias Current, Impedances, and Source

Termination Considerations

The CLC407 has:

If a large source impedance application is considered,

remove all parasitic capacitance around the non-invert-

ing input and source traces.

Parasitic capacitances

near the input and source act as a low-pass filter and

reduce bandwidth.

Current feedback op amps have uncorrelated input

bias currents. These uncorrelated bias currents

prevent source impedance matching on each input

from cancelling offsets.

Refer to application note

OA-07 of the data book to find specific circuits to

correct DC offsets.

Layout Considerations

Whenever questions about layout arise, USE THE

EVALUATION BOARD AS A TEMPLATE.

Use the 730013 and 730026 evaluation boards for the

DIP and SOIC respectively. These board layouts were

optimized to produce the typical performance of the

CLC407 shown in the data sheet. To reduce parasitic

capacitances, the ground plane was removed near

pins 2, 3, and 6. To reduce series inductance, trace

lengths of components and nodes were minimized.

Parasitics on traces degrade performance. Minimize

coupling from traces to both power and ground

planes.

Use low inductance resistors for leaded

components .

Do not use dip sockets for the CLC407 DIP amplifiers.

These sockets can peak the frequency domain

response or create overshoot in the time domain

response.

Use flush-mount socket pins if socketing

cannot be avoided. The 730013 circuit board device

holes are sized for Cambion P/N 450-2598 socket pins

or their functional equivalent.

Figure 3 when driving coaxial cable or a capacitive

load. Use the plot in the typical performance section

labeled “Settling Time vs. Capacitive Load” to determine

itive loads. This optimal resistance improves settling

time for pulse-type applications and increases stability.

Figure 3

SMA

Output

SMA

Input

50

Ω

50

Ω

+5V

-5V

+

+

0.1

µfd

0.1

µfd

6.8

µfd

6.8

µfd

Ω

1

CLC407

7

6

8

5

3

4

2

20k

Ω

20k

Ω

Pin 8

Disable

Pin 4

20k

Ω

Bias

Circuitry

I Tail

Supply

Mid-Point

Pull-up

Resistor

Pin 7

CLC407

NOTE: Pins 4, 7, 8 are external

2

SMA

Output

SMA

Input

50

Ω

50

Ω

R

1

CLC407

7

6

8

5

3

4

2

5

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