AT89C51RD2 / AT89C51ED2 QualPack

Rev. 0 – 2003 July

11

4.3.2 Hot Carriers Injection

Test conditions

The test is performed by forcing a high drain bias on the test device (Vds>Vddmax) to accelerate the carriers to the

maximum. At the same time the gate bias (Vgs) is chosen in order to maximize the injection of carriers into the

gate oxide and also the substrate. WLR_B n-channel W/L 0.35um/25um the stress is performed on a number of

transistors, each at a different stress condition Vds,stress and Vgs,stress. For each transistor, the time to reach the

failure criteria (dIdsat/Idsat=10%) is obtained. NMOS is more sensitive to hot carriers compared to PMOS.

Consequently NMOS is the only structure tested.

Measurement

AT568T7 lot 1J0433 has been measured using the WLR_B hot electron structure with standard drain.

NMOS W/L = 25/0.35 um.

Results

HCI 56.8k 1J0433 AT568T7 FAB 5 N-Channel W/L 0.35/25.0um

10% Change in Idsat

0,0001

0,001

0,01

0,1

1

0,2

0,22

0,24

0,26

0,28

0,3

1/Vdd

Conclusion

The extrapolated life time in the worst case conditions (@Vds=Vdd max & Vgs set to maximize substrate current) is

much greater than 0.2 years in DC mode (qualification requirement) which is equivalent to more than 10 years in

AC mode.