PCI9060ES datasheet(37/192 Pages) ETC

37 / 192 page

SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 28

Version 1.02

3.7 DMA OPERATION

PCI 9080 supports two independent DMA channels

capable of transferring data from the local bus to the PCI

bus or from the PCI bus to the local bus. Each channel

consists of a DMA controller and a programmable FIFO.

Both

channels

support

chaining

and

non-chaining

transfers, Demand Mode DMA, and End of Transfer

(EOT) pins. Master mode must be enabled in the PCI

Command register.

3.7.1 Non-Chaining Mode DMA

The host processor or the local processor sets the local

address, PCI address, transfer count and transfer

direction. The host or local processor then sets a control

bit to initiate the transfer. PCI 9080 will arbitrate the PCI

and local buses and transfer data. Once the transfer is

complete, PCI 9080 sets the “channel done” bit to a

value of 1 and generates an interrupt to the local

processor or the PCI host (programmable). DMA done

bit in the internal DMA register can be pooled to indicate

the status of DMA transfer.

DMA registers are accessible from the PCI bus and local

bus. (Refer to Figure 3-14.)

!"# $

+ ,- !

& -!

' ! !

()

' %&

' *+

, + !

""-'

! %&

Figure 3-14. Non-Chaining DMA Initialization

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