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CS5530 データシート(PDF) 176 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部品番号 CS5530
部品情報  Geode??CS5530 I/O Companion Multi-Function South Bridge
PDF  241 Pages
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メーカー  NSC [National Semiconductor (TI)]
ホームページ  http://www.national.com
Logo NSC - National Semiconductor (TI)

CS5530 データシート(HTML) 176 Page - National Semiconductor (TI)

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176
Revision 4.1
Register Descriptions (Continued)
Index F5h
Second Level Power Management Status Register 2 (RC)
Reset Value = 00h
7
Video Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Video Idle Timer Count Register
(F0 Index A6h)? 0 = No; 1 = Yes.
This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].
SMI generation enabling is at F0 Index 81h[7].
6
User Defined Device 3 (UDEF3) Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the UDEF3
Idle Timer Count Register (F0 Index A4h)? 0 = No; 1 = Yes.
This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].
SMI generation enabling is at F0 Index 81h[6].
5
User Defined Device 2 (UDEF2) Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the UDEF2
Idle Timer Count Register (F0 Index A2h)? 0 = No; 1 = Yes.
This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].
SMI generation enabling is at F0 Index 81h[5].
4
User Defined Device 1 (UDEF1) Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the UDEF1
Idle Timer Count Register (F0 Index A0h)? 0 = No; 1 = Yes.
This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].
SMI generation enabling is at F0 Index 81h[4].
3
Keyboard/Mouse Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Keyboard/Mouse Idle
Timer Count Register (F0 Index 9Eh)? 0 = No; 1 = Yes.
This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].
SMI generation enabling is at F0 Index 81h[3].
2
Parallel/Serial Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Parallel/Serial Port Idle
Timer Count Register (F0 Index 9Ch)? 0 = No; 1 = Yes.
This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].
SMI generation enabling is at F0 Index 81h[2].
1
Floppy Disk Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Floppy Disk Idle Timer Count
Register (F0 Index 9Ah)? 0 = No; 1 = Yes.
This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].
SMI generation enabling is at F0 Index 81h[1].
0
Primary Hard Disk Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Primary Hard Disk Idle
Timer Count Register (F0 Index 98h)? 0 = No; 1 = Yes.
This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].
SMI generation enabling is at F0 Index 81h[0].
Note: This register provides status on the Device Idle Timers to the SMI handler. A bit set here indicates that the device was idle for
the duration configured in the Idle Timer Count register for that device, causing an SMI. Reading this register clears the SMI
status bits. A read-only (mirror) version of this register exists at F0 Index 85h. If the value of the register must be read without
clearing the SMI source (and consequently deasserting SMI), F0 Index 85h may be read instead.
Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit
Description



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