CS5530 datasheet(172/241 Pages) NSC

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Revision 4.1

Index B4h

Floppy Port 3F2h Shadow Register (RO)

Reset Value = xxh

7:0

Floppy Port 3F2h Shadow (Read Only): Last written value of I/O Port 3F2h. Required for support of FDC power

ON/OFF and Zero Volt Suspend/Resume coherency.

This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when

the register is being read. It is provided here to assist in a Save-to-Disk operation.

Index B5h

Floppy Port 3F7h Shadow Register (RO)

Reset Value = xxh

7:0

Floppy Port 3F7h Shadow (Read Only): Last written value of I/O Port 3F7h. Required for support of FDC power

ON/OFF and Zero Volt Suspend/Resume coherency.

This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when

the register is being read. It is provided here to assist in a Save-to-Disk operation.

Index B6h

Floppy Port 1F2h Shadow Register (RO)

Reset Value = xxh

7:0

Floppy Port 1F2h Shadow (Read Only): Last written value of I/O Port 1F2h. Required for support of FDC power

ON/OFF and Zero Volt Suspend/Resume coherency.

This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when

the register is being read. It is provided here to assist in a Save-to-Disk operation.

Index B7h

Floppy Port 1F7h Shadow Register (RO)

Reset Value = xxh

7:0

Floppy Port 1F7h Shadow (Read Only): Last written value of I/O Port 1F7h. Required for support of FDC power

ON/OFF and Zero Volt Suspend/Resume coherency.

This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when

the register is being read. It is provided here to assist in a Save-to-Disk operation.

Index B8h

DMA Shadow Register (RO)

Reset Value = xxh

7:0

DMA Shadow (Read Only): This 8-bit port sequences through the following list of shadowed DMA Controller registers. At

power on, a pointer starts at the first register in the list and consecutively reads incrementally through it. A write to this

register resets the read sequence to the first register. Each shadow register in the sequence contains the last data written

to that location.

The read sequence for this register is:

1. DMA Channel 0 Mode Register

2. DMA Channel 1 Mode Register

3. DMA Channel 2 Mode Register

4. DMA Channel 3 Mode Register

5. DMA Channel 4 Mode Register

6. DMA Channel 5 Mode Register

7. DMA Channel 6 Mode Register

8. DMA Channel 7 Mode Register

9. DMA Channel Mask Register (bit 0 is channel 0 mask, etc.)

10. DMA Busy Register (bit 0 or 1 means a DMA occurred within last 1ms, all other bits are 0)

Index B9h

PIC Shadow Register (RO)

Reset Value = xxh

7:0

PIC Shadow (Read Only): This 8-bit port sequences through the following list of shadowed Programmable Interrupt Con-

troller registers. At power on, a pointer starts at the first register in the list and consecutively reads incrementally through

it. A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the

last data written to that location.

The read sequence for this register is:

1. PIC1 ICW1

2. PIC1 ICW2

3. PIC1 ICW3

4. PIC1 ICW4 - Bits [7:5] of ICW4 are always 0

5. PIC1 OCW2 - Bits [6:3] of OCW2 are always 0 (Note)

6. PIC1 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1

7. PIC2 ICW1

8. PIC2 ICW2

9. PIC2 ICW3

10. PIC2 ICW4 - Bits [7:5] of ICW4 are always 0

11. PIC2 OCW2 - Bits [6:3] of OCW2 are always 0 (Note)

12. PIC2 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1

Note: To restore OCW2 to shadow register value, write the appropriate address twice. First with the shadow register

value, then withthe shadow register valueORedwithC0h.

Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

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