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CS5530 データシート(PDF) 207 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部品番号 CS5530
部品情報  Geode??CS5530 I/O Companion Multi-Function South Bridge
PDF  241 Pages
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メーカー  NSC [National Semiconductor (TI)]
ホームページ  http://www.national.com
Logo NSC - National Semiconductor (TI)

CS5530 データシート(HTML) 207 Page - National Semiconductor (TI)

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Register Descriptions (Continued)
Index 09h-0Bh
PCI Class Code Register (RO)
Reset Value = 0C0310h
This register identifies this function as an OpenHCI device. The Base Class is 0Ch (Serial Bus Controller). The Sub Class is 03h (Uni-
versal Serial Bus). The Programming Interface is 10h (OpenHCI).
Index 0Ch
Cache Line Size Register (R/W)
Reset Value = 00h
This register identifies the system cacheline size in units of 32-bit words. USB will only store the value of bit 3 in this register since the
cacheline size of 32 bytes is the only value applicable to the design. Any value other than 08h written to this register will be read back
as 00h.
If the CS5530 is being used in a GXLV processor based system, this register must be set to 00h.
Index 0Dh
Latency Timer Register (R/W)
Reset Value = 00h
This register identifies the value of the latency timer in PCI clocks for PCI bus master cycles.
Index 0Eh
Header Type Register (RO)
Reset Value = 00h
This register identifies the type of the predefined header in the configuration space. Since USB is a single function device and not a
PCI-to-PCI bridge, this byte should be read as 00h.
Index 0Fh
BIST Register (RO)
Reset Value = 00h
This register identifies the control and status of Built In Self Test. USB does not implement BIST, so this register is read only.
Index 10h-13h
Base Address Register (R/W)
Reset Value = 00000000h
31:12
Base Address: POST writes the value of the memory base address to this register.
11:4
Always 0: Indicates a 4 KB address range is requested.
3
Always 0: Indicates there is no support for prefetchable memory.
2:1
Always 0: Indicates that the base register is 32-bits wide and can be placed anywhere in 32-bit memory space.
0
Always 0: Indicates that the operational registers are mapped into memory space.
Index 14h-3Bh
Reserved
Index 3Ch
Interrupt Line Register (R/W)
Reset Value = 00h
This register identifies which of the system interrupt controllers the devices interrupt pin is connected to. The value of this register is
used by device drivers and has no direct meaning to USB.
Index 3Dh
Interrupt Pin Register (RO)
Reset Value = 01h
This register identifies which interrupt pin a device uses. Since USB uses INTA#, this value is set to 01h.
Index 3Eh
Min. Grant Register (RO)
Reset Value = 00h
This register specifies the desired settings for how long of a burst USB needs assuming a clock rate of 33 MHz. The value specifies a
period of time in units of 1/4 microsecond.
Index 3Fh
Max. Latency Register (RO)
Reset Value = 00h
This register specifies the desired settings for how often USB needs access to the PCI bus assuming a clock rate of 33 MHz. The
value specifies a period of time in units of 1/4 microsecond.
Index 40h-43h
ASIC Test Mode Enable Register (R/W)
Reset Value = 00000000h
Used for internal debug and test purposes only.
Index 44h
ASIC Operational Mode Enable Register (R/W)
Reset Value = 00h
7:1
Write Only: Read as 0s.
0
Data Buffer Region 16: When set the size of the region for the data buffer is 16 bytes. Otherwise, the size is 32 bytes.
Index 45h-FFh
Reserved
Table 4-24. PCIUSB Index xxh: USB Controller Registers (Continued)
Bit
Description



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