CS5530 datasheet(209/241 Pages) NSC

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Revision 4.1

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I/O Port 009h (WO)

Software DMA Request Register, Channels 3:0

7:3

Reserved: Set to 0.

Request Type: 0= Reset; 1= Set.

1:0

Channel Number Request Select: 00 = Channel 0; 01 = Channel 1; 10 = Channel 2; 11 = Channel 3.

I/O Port 00Ah (R/W)

DMA Channel Mask Register, Channels 3:0

7:3

Reserved: Set to 0.

Channel Mask: 0 = Not masked; 1 = Masked

1:0

Channel Number Mask Select: 00 = Channel 0; 01 = Channel 1; 10 = Channel 2; 11 = Channel 3

I/O Port 00Bh (WO)

DMA Channel Mode Register, Channels 3:0

7:6

Transfer Mode: 00 = Demand; 01 = Single; 10 = Block; 11 = Cascade.

Address Direction: 0 = Increment; 1 = Decrement.

Auto-initialize: 0 = Disable; 1 = Enable.

3:2

Transfer Type: 00 = Verify; 01 = Memory read; 10 = Memory write; 11 = Reserved.

1:0

Channel Number Mode Select: 00 = Channel 0; 01 = Channel 1; 10 = Channel 2; 11 = Channel 3.

I/O Port 00Ch (WO)

DMA Clear Byte Pointer Command, Channels 3:0

I/O Port 00Dh (WO)

DMA Master Clear Command, Channels 3:0

I/O Port 00Eh (WO)

DMA Clear Mask Register Command, Channels 3:0

I/O Port 00Fh (WO)

DMA Write Mask Register Command, Channels 3:0

I/O Port 0C0h (R/W)

DMA Channel 4 Address Register

Not used.

I/O Port 0C2h (R/W)

DMA Channel 4 Transfer Count Register

Not used.

I/O Port 0C4h (R/W)

DMA Channel 5 Address Register

Memory address bytes 1 and 0.

I/O Port 0C6h (R/W)

DMA Channel 5 Transfer Count Register

Transfer count bytes 1 and 0

I/O Port 0C8h (R/W)

DMA Channel 6 Address Register

Memory address bytes 1 and 0.

I/O Port 0CAh (R/W)

DMA Channel 6 Transfer Count Register

Transfer count bytes 1 and 0.

I/O Port 0CCh (R/W)

DMA Channel 7 Address Register

Memory address bytes 1 and 0.

I/O Port 0CEh (R/W)

DMA Channel 7 Transfer Count Register

Transfer count bytes 1 and 0.

Table 4-25. DMA Channel Control Registers (Continued)

Bit

Description

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