www.ti.com

DESCRIPTION/ORDERING INFORMATION (CONTINUED)

TG

C

C

TG

C

C

TG

C

C

C

TG

C

C

PRE

CLK

D

CLR

Q

Q

C

7

2

6

5

3

1

SN74LVC2G74

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

SCES203K – APRIL 1999 – REVISED JUNE 2005

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,

data at the D input can be changed without affecting the levels at the outputs.

preventing damaging current backflow through the device when it is powered down.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK

D

Q

Q

L

H

X

X

H

L

H

L

X

X

L

H

L

L

X

X

H

H

↑

H

H

L

H

H

↑

L

L

H

H

H

L

X

(1)

This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive

(high) level.

LOGIC DIAGRAM (POSITIVE LOGIC)

2