SiP823/SiP824/SiP825

Vishay Siliconix

www.vishay.com

4

Document Number: 72397

S-41150—Rev. B, 14-Jun-04

PIN DESCRIPTION

SiP823

SiP824

SiP825

Name

Description

1

1

1

RESET

RESET is active low. This pin has a push/pull output.

2

2

2

GND

Ground

N/A

3

3

RESET

RESET is active high. This pin has a push/pull output.

3

N/A

4

MR

Manual RESET. Active low. Pulling this pin low forces a RESET. After a low to high transition RESET

remains asserted for exactly one RESET timed period. This pin is internally pulled high. If this function is

4

4

N/A

Watchdog Input. Any transition on this pin will RESET the watchdog timer. If this pin remains high or low

for longer than the watchdog interval, a RESET is asserted. Float or tristate this pin to disable the

watchdog feature.

5

5

5

Positive power supply. A RESET is asserted after this voltage drops below a predetermined level. After

TIMING DIAGRAMS

50%

50%

50%

50%

RESET

RESET

Figure 1.

RESET Timing Diagram

Figure 2.

Watchdog Timing Diagram

WDI