PC33889

21

PC33889

7

SPI INTERFACE

7.1

Data format description

The SPI is a 8 bit SPI. First 3 bits are used to identify the internal SBC register address, bit 4 is a read/write bit. The last 4 bits

are data send from MCU to SBC or read back from SBC to MCU.

During write operation state of MISO has no signification.

During read operation only the last 4 bits at MISO have a meaning (content of the accessed register)

Following tables describe the SPI register list, and register bit meaning.

Registers “reset value” is also described, as well as the “reset condition”. reset condition is the condition which cause the bit

to be set at the “reset value”.

Possible reset condition are:

Power On Reset: POR

SBC mode transition:

NR2R - Normal Request to Reset mode

NR2N - Normal Request to Normal mode

N2R - Normal to Reset mode

STB2R - Standby to Reset mode

STO2R - Stop to Reset mode

SBC mode:

RESET - SBC in Reset mode

List of Registers

Name

Adress

Description

Comment and usage

MCR

$ 0 0 0

Mode control register

Write: Control of normal, standby, sleep, and stop modes

Read: BATFAIL flag and other status bits and flags

RCR

$ 0 0 1

Reset control register

Write: Configuration of reset voltage level, WD in stop mode, low

power mode selection

Read: CAN wake up event, Tx permanent dominant

CAN

$ 0 1 0

CAN control register

Write: CAN module control: Tx/Rx, Rec only, term Vbat, Normal and

extended modes, filter at L0 input.

Read: CAN failure status bits

IOR

$ 0 1 1

I/O control register

Write: HS1 (high side switch) control in normal and standby mode.

Gnd shift register level selection

Read: HS1 over temp bit, SHIFT bit (gnd shift above selection), Vsup

below 6.1V, V2 below 4V

WUR

$ 1 0 0

Wake up input register

Write: Control of wake up input polarity

Read: Wake up input, and real time Lx input state

TIM

$ 1 0 1

Timing register

Write: TIM1, Watchdog timing control, window or Timeout mode.

Write: TIM2, Cyclic sense and force wake up timing selection

LPC

$ 1 1 0

Low power mode

control register

Write: HS1 periodic activation in sleep and stop modes

Force wake up control

INTR

$ 1 1 1

Interrupt register

Write: Interrupt source configuration

Read: INT source

Table 7-1.

MOSI

MISO

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

D0

D1

D2

D3

R/W

A0

A1

A2

data

address

Read operation: R/W bit = 0

Write operation: R/W bit = 1

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com