TLF6381

June 1989

DM74LS90DM74LS93

Decade and Binary Counters

General Description

Each of these monolithic counters contains four master-

slave flip-flops and additional gating to provide a divide-by-

two counter and a three-stage binary counter for which the

count cycle length is divide-by-five for the ’LS90 and divide-

by-eight for the ’LS93

All of these counters have a gated zero reset and the LS90

also has gated set-to-nine inputs for use in BCD nine’s com-

plement applications

To use their maximum count length (decade or four bit bina-

count pulses are applied to input A and the outputs are as

described in the appropriate truth table A symmetrical di-

vide-by-ten count can be obtained from the ’LS90 counters

input count to the B input which gives a divide-by-ten square

Features

Y

Typical power dissipation 45 mW

Y

Count frequency 42 MHz

TLF6381 – 1

Order Number DM74LS90M or DM74LS90N

See NS Package Number M14A or N14A

TLF6381 – 2

Order Number DM74LS93M or DM74LS93N

See NS Package Number M14A or N14A

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A