DAC8564IDPWR datasheet(5/51 Pages) TI1

5 / 51 page

OUT

LDAC

ENABLE

DAC8564

OUT

H/V

OUT

REF

GND

OUT

IOV

SCLK

SYNC

DAC8564

www.ti.com

SBAS403D

– JUNE 2007 – REVISED MAY 2011

PIN CONFIGURATIONS

PW PACKAGE

TSSOP-16

(Top View)

PIN DESCRIPTIONS

NAME

DESCRIPTION

VOUTA

Analog output voltage from DAC A

VOUTB

Analog output voltage from DAC B

VREFH/

Positive reference input / reference output 2.5V if internal reference used.

VREFOUT

AVDD

Power-supply input, 2.7V to 5.5V

VREFL

Negative reference input

GND

Ground reference point for all circuitry on the part

VOUTC

Analog output voltage from DAC C

VOUTD

Analog output voltage from DAC D

Level-triggered control input (active low). This input is the frame synchronization signal for the input data. When SYNC

goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output

SYNC

updates following the 24th clock. If SYNC is taken high before the 24th clock edge, the rising edge of SYNC acts as

an interrupt, and the write sequence is ignored by the DAC8564. Schmitt-Trigger logic input.

SCLK

Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic input.

Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock input.

DIN

Schmitt-Trigger logic input.

IOVDD

Digital input-output power supply

Address 0

—sets device address; see Table 5.

Address 1

—sets device address; see Table 5.

ENABLE

The enable pin (active low) connects the SPI interface to the serial port

LDAC

Load DACs; rising edge triggered, loads all DAC registers

DAC8564IDPWR データシート(PDF) 5 Page - Texas Instruments

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