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AD1837AS データシート(PDF) 13 Page - Analog Devices |
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AD1837AS データシート(HTML) 13 Page - Analog Devices |
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13 / 24 page ![]() REV. B AD1837 –13– CLATCH CCLK CIN COUT D0 D8 D0 D15 D14 D9 D8 t CCH tCCL D9 t CDS tCDH t CLS t CLH t COD t COTS t CCP t COE Figure 3. Format of SPI Timing LRCLK BCLK SDATA LRCLK BCLK SDATA LRCLK BCLK SDATA LRCLK BCLK SDATA LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL MSB MSB MSB MSB MSB MSB MSB MSB LSB LSB LSB LSB LSB LSB LSB LSB LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL I2S MODE—16 BITS TO 24 BITS PER CHANNEL RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL DSP MODE—16 BITS TO 24 BITS PER CHANNEL 1/ fS NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL. 2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH IS 2 fS. 3. BCLK FREQUENCY IS NORMALLY 64 LRCLK BUT MAY BE OPERATED IN BURST MODE. Figure 4. Stereo Serial Modes |
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