AD6635BBSLASHPCB datasheet(39/60 Pages) AD

39 / 60 page

REV. 0

AD6635

–39–

both. Bits 1 and 2 of register addresses 0x1A and 0x1C control

the inclusion of data from AGCs A and B, respectively. Simi-

larly, Parallel Ports C and D can provide data from either

AGC C, AGC D, or both.

AGC mode provides only one I and Q format, which is similar

to the 16-bit Interleaved format of Channel mode. When both

REQ and ACK are asserted, the next rising edge of PCLK

triggers the output of a 16-bit AGC I word for one PCLK cycle.

The PxIQ (x = A, B, C, or D) output indicator pins are high

during this cycle, and low otherwise. A 16-bit AGC Q word is

provided during the subsequent PCLK cycle. If the AGC gain

word has been updated since the last sample, a 12-bit RSSI

word (Receive Signal Strength Indicator) is provided during the

PCLK cycle following the Q word on the 12 MSBs of the paral-

lel port data pins. The RSSI word is the bit inverse of the signal

gain word used in the gain multiplier of the AGC.

The data provided by the PACH[1:0] and PBCH[1:0] pins in

AGC mode is different than that provided in Channel mode. In

AGC mode, PACH[0] and PBCH[0] indicate the AGC source

of the data currently being output (0 = AGC A, 1 = AGC B).

PACH[1] and PBCH[1] indicate whether the current data is an

I/Q word or an AGC RSSI word (0 = I/Q word, 1 = AGC RSSI

word). The two different AGC outputs are shown in Figures 37

and 38.

I[15:0]

Q[15:0]

PxCH[0] = AGC NO.

PxCH[1] = 0

tDPCH

tDPP

PCLKn

PxREQ

Px[15:0]

PxACK

PxlQ

PxCH[1:0]

tDPIQ

tDPREQ

Figure 37. AGC with No RSSI Word

PxCH[0] = AGC NO.

PxCH[1] = 0

PxCH[0] = AGC NO.

PxCH[1] = 1

tDPP

PCLKn

PxREQ

Px[15:0]

PxACK

PxlQ

PxCH[1:0]

I[15:0]

Q[15:0]

RSSI[11:0]

tDPREQ

tDPIQ

tDPCH

Figure 38. AGC with RSSI Word

Master/Slave PCLKn Modes

The parallel ports may operate in either Master or Slave mode.

The mode is set via the Port Clock Control register (address

0x1E). The parallel ports power up in Slave mode to avoid

possible contentions on the PCLKn pin. Parallel Ports A and B

can be set up in Master mode while Ports C and D are set up in

Slave mode, or vice versa. But, both the Ports A and B, or C

and D, should be in the same mode, since they share the paral-

lel port clock PCLK0 and PCLK1, respectively.

In Master mode, PCLK is an output whose frequency is the

AD6635 clock frequency divided by the PCLK divisor. Since

values for PCLK_divisor [2:1] can be set to 0, 1, 2, or 3, integer

divisors of 1, 2, 4, or 8, respectively, can be obtained. Since the

maximum clock rate of the AD6635 is 80 MHz, the highest

PLCK rate in Master mode is also 80 MHz. Master mode is

selected by setting Bit 0 of address 0x1E.

In Slave mode, external circuitry provides the PCLK signal.

Slave mode PCLK signals may be either synchronous or

asynchronous. The maximum Slave mode PCLK frequency

is 100 MHz.

Parallel Port Pin Functionality

The following describes the functionality of the pins used by the

parallel ports.

PCLK: Input/output. As an output (Master mode), the maxi-

mum frequency is CLK/N, where CLK is the AD6635 clock

and N is an integer divisor of 1, 2, 4, or 8. As an input (Slave

mode), it may be asynchronous relative to the AD6635 CLK.

This pin powers up as an input to avoid possible contentions.

Other port outputs change on the rising edge of PCLK.

REQ: Active high output, synchronous to PCLK. A logic high

on this pin indicates that data is available to be shifted out of

the port. The logic level remains high until all pending data has

been shifted out.

ACK: Active high asynchronous input. Applying a logic low on

this pin inhibits parallel port data shifting. Applying a logic high

to this pin when REQ is high causes the parallel port to shift out

data according to the programmed data mode. ACK is sampled

on the rising edge of PCLK. Assuming REQ is asserted, the

latency from the assertion of ACK to data appearing at the

parallel port output is no more than 1.5 PCLK cycles (see

Figure 12). ACK may be held high continuously; in this case,

when data becomes available, shifting begins one PCLK cycle

after the assertion of REQ (see Figures 35, 36, and 37).

PAIQ, PBIQ, PCIQ, PDIQ: High whenever I data is present

on the port output, low otherwise.

PxCH[1:0], PxCH[1:0], PCCH[1:0], PDCH[1:0]: These pins

serve to identify data in both of the data modes. In Channel

mode, these pins form a 2-bit binary number identifying the

source channel of the current data word. In AGC mode, [0]

indicates the AGC source (0 = AGC A, 1 = AGC B), and [1]

indicates whether the current data word is (0 = I/Q data) or

(1 = RSSI word). Similarly for parallel Ports C and D, [0]

indicates the AGC source (0 = AGC C, 1 = AGC D), and [1]

indicates whether the current data word is (0 = I/Q data) or

(1 = RSSI word).

PA[15:0], PB[15:0], PC[15:0], PD[15:0]: Parallel output data

ports. Contents and format are mode dependent.

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