CP3SP33SMSSLASHNOPB datasheet(91/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

NMOD

The N Mod field specifies the fractional part of the N divisor. See Section 14.4.1 PLL

Programming for more information.

NMOD_DITH

The N Mod Dithering field specifies the level of dithering to be applied to the PLL Clock

to suppress tone artifacts that may occur in some audio applications. The default level

is sufficient for a wide range of applications.

00 – Medium (default).

01 – Low.

10 – High.

11 – No dithering.

14.8.11 PLLn P Divider Register (PMMPLLnPDIV)

The PMMPLLnPDIV registers are byte-wide, read/write registers that hold the 8-bit P divisor for the

corresponding PLL. The register is initialized to 00h at reset.

PDIV

The P Divisor field specifies an integer divisor. See Section 14.4.1 PLL Programming for more

information.

14.8.12 PLLn Start-Up Counter Register (PMMPLLnSTUP)

The PMMPLLnSTUP registers are 16-bit, read/write registers that specify a 10-bit integer number of clock

periods that must occur before the corresponding PLL Clock is considered stable. The PLL Clock output is

not driven unless the PLL is stable and the PMMPLLnCTL1.PLLDCOE bit is set. The registers are

initialized to 007Fh at reset.

10M M9

Reserved

CLKCNT

CLKCNT The CLKCNT field specifies the number of PLL Clock cycles which must occur before the PLL

is considered stable. The number of cycles is (256 × (CLKCNT + 1)), therefore the default is

32,768 cycles.

14.8.13 Auxiliary Clock n Control Register (PMMAUXnCTL)

The PMMAUXnCTL registers are byte-wide, read/write registers that control the Auxiliary Clock

generators. The registers are initialized to 06h at reset, except PMMAUX7CTL which is initialized to 07h.

3 2

Reserved

AUXCLKSRC

AUXCLKEN

The Auxiliary Clock Enable bit enables the corresponding Auxiliary Clock output.

0 – PLL Clock output disabled.

1 – PLL Clock is enabled when stable.

AUXCLKSRC

The Auxiliary Clock Source field selects the input clock source for the corresponding

Auxiliary Clock generator. When switching from one PLL to another, there must be an

intermediate step in which Main Clock is selected.

00 – PLL1 Clock.

01 – PLL2 Clock.

10 – Reserved.

11 – Main Clock.

Clock Generation

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