DS90C187

SNLS401B – FEBRUARY 2012 – REVISED APRIL 2013

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Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Min

Typ

Max

Unit

TSTC

INn_x Setup to IN_CLK

Figure 7

0

ns

THTC

INn_x Hold from IN_CLK

2.5

ns

LLHT

LVDS Low-to-High Transition Time

0.18

0.5

ns

Figure 5 (1)

LHLT

LVDS High-to-Low Transition Time

0.18

0.5

ns

Figure 5 (1)

TBIT

LVDS Output Bit Width

MODE[1:0] = 00, or 10

1/7 TCIP

ns

MODE[1:0] = 01

2/7 TCIP

ns

TPPOS0

Transmitter Output Pulse Positions Normalized

Figure 10

1

UI

for Bit 0

TPPOS1

Transmitter Output Pulse Positions Normalized

2

UI

for Bit 1

TPPOS2

Transmitter Output Pulse Positions Normalized

3

UI

for Bit 2

TPPOS3

Transmitter Output Pulse Positions Normalized

4

UI

for Bit 3

TPPOS4

Transmitter Output Pulse Positions Normalized

5

UI

for Bit 4

TPPOS5

Transmitter Output Pulse Positions Normalized

6

UI

for Bit 5

TPPOS6

Transmitter Output Pulse Positions Normalized

7

UI

for Bit 6

ΔTPPOS

Variation in Transmitter Pulse Position (Bit 6 —

±0.06

UI

Bit 0)

TCCS

LVDS Channel to Channel Skew

110

ps

TJCC

Jitter Cycle-to-Cycle

MODE0, MODE1 = 0,

0.028

0.035

UI

f = 105 MHz,

(1)

TPLLS

Phase Lock Loop Set (Enable Time)

Figure 8

1

ms

TPDD

Powerdown Delay

Figure 9

100

ns

(2)

TSD

Latency Delay

MODE0 = 0,

2*TCIP +

2*TCIP +

ns

MODE1 = 1 or 0

10.54

13.96

Figure 11

(1)

TLAT

Latency Delay for Single Pixel In / Dual Pixel Out MODE0 = 1,

9*TCIP +

9*TCIP +

ns

Mode

MODE1 = 0

4.19

6.36

Figure 11

(1)

(1)

Parameter is guaranteed by characterization and is not tested at final test.

(2)

Parameter is guaranteed by design and is not tested at final test.

8

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