LM2512A

SNLS269B – AUGUST 2007 – REVISED MAY 2013

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When using the auto power down mode, the PD* input needs to be held High. When the PCLK is held static, the

SER will detect this condition and power down. When the PCLK is restarted, the SER powers up, The DES is

calibrated, and the PLL locks to the incoming clock signal. Once this is complete, video data transmission can

occur. See Figure 3, Figure 4, and Figure 9. The stopping of the pixel clock should be done cleanly. The

minimum clock stop gap should be at least 4 PCLK cycles wide. Floating of the PCLK input pin is not

recommended. Consult the MPL DES datasheet to determine requirements that the DES requires.

LM2512A vs LM2512

The following list provides the differences between the LM2512 and the enhanced LM2512A.

•

Increased Idata Current

•

Enhanced Current Matching

•

Enhanced MC Duty Cycle

•

2 MD Lane Default Configuration

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Dither Off Default

•

•

MPL Driver Edge Rate Control Option

APPLICATION INFORMATION

SYSTEM BANDWIDTH CALCULATIONS

For a HVGA (320 X 480) application with the following assumptions: 60 Hz +/

−5% refresh rate, 10% blanking,

RGB666, and 2 MD Lanes and following calculations can be made:

Calculate PCLK - 320 X 480 X 1.1 X 60 X 1.05 = 10.6 MHz PCLK

Calculate MC rate - since the application is 2 MD lanes, PCLK X 6 is the MC rate or 63.87 MHz. Also check that

this MC rate does not exceed the MC maximum rate for the chipset.

Calculate MD rate - MPL uses both edges of the MC to send serialized data, thus data rate is 2X the MC rate, or

127.7 Mbps per MD lane in our example.

Calculate the application throughput - using 2 MD lanes, throughput is 2 X of the MD rate or 255.5 Mbps of raw

band width.

For a VGA (640 X 480) application with the following assumptions: 55 Hz +/

−5% refresh rate, 10% blanking,

RGB666, and 3 MD Lanes and following calculations can be made:

Calculate PCLK - 640 X 480 X 1.1 X 55 X 1.05 = 19.5 MHz PCLK

Calculate MC rate - since the application is 3 MD lanes, PCLK X 4 is the MC rate or 78.1 MHz. Also check that

this MC rate does not exceed the MC maximum rate for the chipset.

Calculate MD rate - MPL uses both edges of the MC to send serialized data, thus data rate is 2X the MC rate, or

156 Mbps per MD lane in our example.

Calculate the application throughput - using 3MD lanes, throughput is 3X of the MD rate or 468 Mbps of raw

band width.

SYSTEM CONSIDERATIONS

When employing the MPL SER/DES chipset in place of a parallel video bus, a few system considerations must

be taken into account. Before sending video data to the display, the SER/DES must be ready to transmit data

across the link. The MPL link must be powered up, and the PLL must be locked and the DES calibrated.

FLEX CIRCUIT RECOMMENDATIONS

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