DP83932C datasheet(49/98 Pages) NSC

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50 Bus Interface (Continued)

TABLE 5-1 Pin Description

(Continued)

Symbol

Driver

Direction

Description

Type

BUS INTERFACE PINS

(Continued)

Chip Select

The system asserts this pin low to access the SONIC’s registers The

registers are selected by placing an address on lines RA5 – RA0

Note

Both CS and MREQ must not be asserted concurrently If these signals are

successively asserted there must be at least two bus clocks between the deasserting

edge of the first signal and the asserting edge of the second signal

SAS

Slave Address Strobe

The system asserts this pin to latch the register address on

lines RA0 – RA5 When BMODE e 1 the address is latched on the falling edge of SAS

When BMODE e 0 the address is latched on the rising edge of SAS

SRW

The system asserts this pin to indicate whether it will read from or write to the SONIC’s

SWR

registers

Slave ReadWrite (SRW)

When BMODE e 1 this signal is asserted high during a

read and low during a write

Slave WriteRead (SWR)

when BMODE e 0 this signal is asserted low during a read

and high during a write

TRI

O Z

Data Strobe

When the SONIC is bus master it drives this pin low during a read cycle to

indicate that the slave device may drive data onto the bus in a write cycle this pin

indicates that the SONIC has placed valid data onto the bus

DSACK0

TRI

I O Z

Data and Size Acknowledge 0 and 1

(DSACK01 BMODE e 1) These pins are the

RDYi

output slave acknowledge to the system when the SONIC registers have been

DSACK1

TRI

I O Z

accessed and the input slave acknowledgement when the SONIC is busmaster When a

RDYo

terminate the slave cycle (Note that the SONIC responds as a 32-bit peripheral by

driving both DSACK0 and DSACK1 low but drives data only on lines D0 – D15 Lines

D16 – D31 are driven but invalid) When the SONIC is bus master it samples these pins

before terminating its memory cycle When SONIC is in 32-bit bus master mode both

DSACK0 and DSACK1 must be asserted to terminate the cycle However if the SONIC

is in 16-bit bus master mode only the assertion of DSACK1 is required to terminate the

cycle These pins are sampled synchronously or asynchronously depending on the state

of the SBUS bit in the Data Configuration register See Section 545 for details Note

that the SONIC does not allow dynamic bus sizing Bus size is statically defined in the

Data Configuration register (see Section 432)

Ready Input

(RDYi BMODE e 0) When the SONIC is a bus master the system

asserts this signal high to insert wait-states and low to terminate the memory cycle This

signal is sampled synchronously or asynchronously depending on the state of the SBUS

bit See Section 545 and 432 for details

Ready Output

(RDYo BMODE e 0) When a register is accessed the SONIC asserts

this signal to terminate the slave cycle

BRT

Bus Retry

When the SONIC is bus master the system asserts this signal to rectify a

potentially correctable bus error This pin has 2 modes Mode 1 (the LBR in the Data

Configuration register is set to 0) Assertion of this pin forces the SONIC to terminate

the current bus cycle and will repeat the same cycle after BRT has been deasserted

Mode 2 (the LBR bit in the Data Configuration register is set to 1) Assertion of this

signal forces the SONIC to retry the bus operation as in Mode 1 However the SONIC

will not continue DMA operations until the BR bit in the ISR is reset

ECS

TRI

O Z

Early Cycle Start

This output gives the system earliest indication that a memory

operation is occurring This signal is driven low at the rising edge of T1 and high at the

falling edge of T1

DP83932C データシート(PDF) 49 Page - National Semiconductor (TI)

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