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TAS3208IPZP データシート(PDF) 50 Page - Texas Instruments

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部品番号 TAS3208IPZP
部品情報  DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
PDF  79 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

TAS3208IPZP データシート(HTML) 50 Page - Texas Instruments

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S
SCL
t
HD;DAT
t
SU;DAT
t
LOW
t
HD;STA
t
HD;STA
t
SP
t
BUF
t
f
t
f
t
r
t
r
t
HIGH
t
SU;STA
t
SU;STO
SDA
S
Sr
P
TAS3208
SLES201E
– JANUARY 2007 – REVISED MARCH 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 38. I2C SCL and SDA Timing
Master I
2C Load RAM Block Formats
This section describes the format of the data that is stored in an external memory device and downloaded to the
TAS3208 via the master I2C bus.
Master I2C Memory Block Header
Table 11. 1 Memory Block Header
STARTING
DATA BLOCK FORMAT
SIZE
NOTES
BYTE
Checksum MSB
0
2 bytes
Checksum of byte 2 through N + 12
Checksum LSB
Header ID byte 1 = 0x00
2
2 bytes
Must be 0x001F
Header ID byte 2 = 0x1F
0x00: Microprogram RAM or termination header
0x01: Micro external data RAM
0x02: DSP program RAM
4
Memory to be loaded
1 byte
0x03 : DSP coefficient RAM
0x04: DSP data RAM
0x05
–0x0F: Reserved
5
0x00
1 byte
Unused
Start memory address MSB
6
2 bytes
If this is a termination header, this value is 0000.
Start memory address LSB
Total number of byte transferred MSB
Header size (12) + data byte + last checksum byte. If this is
8
2 bytes
a termination header, this value is 0000.
Total number of byte transferred LSB
10
0x00
1 byte
Unused
11
0x00
1 byte
Unused
50
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Copyright
© 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TAS3208



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