23A1024-ESLASHSTSLASHP datasheet(10/32 Pages) MICROCHIP

部品番号	23A1024-E/ST/P

部品情報	1Mbit SPI Serial SRAM with SDI and SQI Interface

PDF	32 Pages

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メーカー	MICROCHIP [Microchip Technology]

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10 / 32 page

23A1024/23LC1024

DS20005142C-page 10

 2012-2015 Microchip Technology Inc.

2.5

Read Mode Register Instruction

(RDMR)

The Read Mode Register instruction (RDMR) provides

access to the MODE register. The MODE register may

be read at any time. The MODE register is formatted as

follows:

TABLE 2-2:

MODE REGISTER

The mode bits indicate the operating mode of the

SRAM. The possible modes of operation are:

0 0

= Byte mode

1 0

= Page mode

0 1

= Sequential mode (default operation)

1 1

= Reserved

Bits 0 through 5 are reserved and should always be set

to ‘0’.

See Figure 2-7 for the RDMR timing sequence.

FIGURE 2-7:

READ MODE REGISTER TIMING SEQUENCE (RDMR)

W/R

–

MODE

W/R = writable/readable

1011

12131415

Instruction

Data from MODE Register

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