CS8413 datasheet(31/38 Pages) ETC

31 / 38 page

CS8413 CS8414

DS240F1

Audio Output Interface

SCK - Serial Clock, PIN 12.

Serial clock for SDATA pin which can be configured (via the M0, M1, M2, and M3 pins) as

an input or output, and can sample data on the rising or falling edge. As an output, SCK will

generate 32 clocks for every audio sample. As an input, 32 SCK periods per audio sample must

be provided in all normal modes.

FSYNC - Frame Sync, PIN 11.

Delineates the serial data and may indicate the particular channel, left or right, and may be an

input or output. The format is based on M0, M1, M2, and M3 pins.

SDATA - Serial Data, PIN 26.

Audio data serial output pin.

M0, M1, M2, M3 - Serial Port Mode Select, PINS 23, 24, 18, 17.

Selects the format of FSYNC and the sample edge of SCK with respect to SDATA. M3 selects

between eight normal modes (M3 = 0), and six special modes (M3 = 1).

Control Pins

VERF - Validity + Error Flag, PIN 28.

A logical OR’ing of the validity bit from the received data and the error flag. May be used by

interpolation filters to interpolate through errors.

U - User Bit, PIN 14.

Received user bit serial output port. FSYNC may be used to latch this bit externally. (Except in

I2S modes when this pin is updated on the active edge of FSYNC.)

C - Channel Status Output, PIN 1.

Received channel status bit serial output port. FSYNC may be used to latch this bit externally.

(Except in I2S modes when this pin is updated on the active edge of FSYNC.)

CBL - Channel Status Block Start, PIN 15.

The channel status block output is high for the first four bytes of channel status and low for the

last 20 bytes.

SEL - Select, PIN 16.

Control pin that selects either channel status information (SEL = 1) or error and frequency

information (SEL = 0) to be displayed on six of the following pins.

CS8413 データシート(PDF) 31 Page - List of Unclassifed Manufacturers