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CY2210
Document #: 38-07204 Rev. *A
Page 3 of 10
Notes:
2.
TCLK is a test clock driven in on the XTALIN input in test mode.
3.
Only CY2210-2 supports this option. In CY2210-3, this selection is defined as “N/A” or “Reserved”.
Function Table[2]
SEL133
SEL1
SEL0
CPUCLK
(MHz)
CPUCLK/2
(MHz)
AGPCLK
(MHz)
PCICLK
(MHz)
USBCLK
(MHz)
REFCLK
(MHz)
APICCLK
(MHz)
0
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
1
100.227[3]
50.114[3]
66.818[3]
33.409[3]
48.008[3]
14.318[3]
16.705[3]
0
1
0
100
50
66.67
33.33
OFF
14.318
16.67
0
1
1
100
50
66.67
33.33
48
14.318
16.67
1
0
0
TCLK/2
TCLK/4
TCLK/4
TCLK/8
TCLK/2
TCLK
TCLK/16
1
0
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
1
0
133.33
66.67
66.67
33.33
OFF
14.318
16.67
1
1
1
133.33
66.67
66.67
33.33
48
14.318
16.67
Actual Clock Frequency Values
Clock
Output
Target
Frequency
(MHz)
Actual
Frequency
(MHz)
PPM
-2
-3
-4
-2
-3
-4
-2
-3
-4
CPUCLK
100.0
100.0
100.0
99.126
99.126
100.227
–8740
–8740
+2714
CPUCLK
133.33
133.33
133.33
132.769
132.769
132.769
–4208
–4208
–4208
USBCLK
48.0
48.0
48.0
48.008
48.008
48.008
167
167
167
Clock Enable Configuration
CPU_STOP
PWR_DWN
PCI_STOP
CPUCLK
CPUCLK/2
AGP
PCI
PCI_F
REF
APIC
OSC.
VCOs
X
0
X
LOW
LOW
LOW
LOW
LOW
LOW
OFF
OFF
0
1
0
LOW
ON
LOW
LOW
ON
ON
ON
ON
0
1
1
LOW
ON
LOW
ON
ON
ON
ON
ON
1
1
0
ON
ON
ON
LOW
ON
ON
ON
ON
1
1
1
ON
ON
ON
ON
ON
ON
ON
ON
Clock Driver Impedances
Impedance
Buffer Name
VDD Range
Buffer Type
Minimum
Ω
Typical
Ω
Maximum
Ω
CPU, CPU/2, APIC
2.375–2.625
Type 1
13.5
29
45
USB, REF
3.135–3.465
Type 3
20
40
60
PCI, AGP
3.135–3.465
Type 5
12
30
55
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