TLK2201BRCPR datasheet(13/24 Pages) TI1

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CLOCK

80%

50%

20%

0.8V

DATA

1.4V

LVTTL OUTPUT SWITCHING CHARACTERISTICS

TRANSMITTER TIMING REQUIREMENTS

TLK2201B

TLK2201BI

SLLS585C – NOVEMBER 2003 – REVISED FEBRUARY 2008

Figure 9. TTL Data I/O Valid Levels for AC Measurement

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tr(RBC)

Clock rise time

80% to 20% output voltage, C = 5 pF (see Figure 9)

0.3

1.5

tf(RBC)

Clock fall time

0.3

1.5

Data rise timer

0.3

1.5

Data fall time

0.3

1.5

Data setup time (RD0..RD9),

tsu(D1)

TBI normal mode (see Figure 3)

2.5

Data valid prior to RBC0 rising)

Data hold time (RD0..RD9),

th(D1)

TBI normal mode (see Figure 3)

Data valid after RBC0 rising

tsu(D2)

Data setup time (RD0..RD4)

DDR mode, Rω = 125 MHz (see Figure 4)

th(D2)

Data hold time (RD0..RD4)

DDR mode, Rω = 125 MHz (see Figure 4)

0.8

tsu(D3)

Data setup time (RD0..RD9)

TBI half-rate mode, Rω = 125 MHz (see Figure 2)

2.5

th(D3)

Data hold time (RD0..RD9)

TBI half-rate mode, Rω = 125 MHz (see Figure 2)

1.5

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tsu(D4)

Data setup time (TD0..TD9)

1.6

TBI modes

th(D4)

Data hold time (TD0..TD9)

0.59(1)

tsu(D5)

Data setup time (TD0..TD9)

0.7

DDR modes

th(D5)

Data hold time (TD0..TD9)

0.5

tr, tf

TD[0,9] Data rise and fall time

See Figure 9

(1)

Measured at 1.25V (midpoint of VIL and VIH) with input switching between 0V and VDD.

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