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CY7C68310
Document 38-08030 Rev. *H
Page 4 of 34
63
nDIOR
O
3.3V drive,
5V-tolerant,
6 mA IOL
ATA control signal.
64
IORDY
I
5V-tolerant
Schmitt input
ATA control signal.
65
ATAPUEN
O
3.3V drive,
5V-tolerant,
6 mA IOL
ATA IORDY pull-up connection. For VBUS-powered systems.
66
nDMACK
O
3.3V drive,
5V-tolerant,
6 mA IOL
ATA control signal.
67
ATAIRQ
I
5V-tolerant
Schmitt input
ATA interrupt request.
70, 68, 71
DA[0:2]
O
3.3V drive,
5V-tolerant,
6 mA IOL
ATA address signals.
72, 73
nCS[0:1]
O
3.3V drive,
5V-tolerant,
6 mA IOL
ATA chip select signals.
74
nPWR500
O
high-Z driver,
5V-tolerant,
6 mA IOL
Active LOW. VBUS power granted indicator.
‘0’ = VBUS power up to bMaxPower value
‘high-Z’ = bMaxPower value not granted (if more than 100 mA)
75
SCL
O
high-Z driver,
5V-tolerant,
6 mA IOL
I2C-compatible clock. This pin may be left as a no-connect pin if
the I2C-compatible interface is not utilized.
76
SDA_nlMODE
I/O
high-Z driver,
5V-tolerant,
6 mA IOL,
Schmitt input
I2C-compatible address/data or nIMODE select.
77
DISKRDY
I
5V-tolerant
Schmitt input
Configurable polarity. Device ready.
78
VBUSPWRD
I
5V-tolerant
Schmitt input
Active HIGH. Bus-powered operation select pin.
‘1’ = Bus powered
‘0’ = Self powered
79
VBUSPWRVLD
I
5V-tolerant
Schmitt input
Active HIGH. Indicates that VBUS power is present.
1, 4, 10,
21, 47, 60
VSS
Power
Digital ground.
3, 17, 40,
59, 80
VDD25
Power
2.5V digital supply.
7, 24, 50,
61, 69
VDD33
Power
3.3V digital supply.
11
PVDD25
Power
Analog 2.5V supply (PLL).
12,14,16
AVSS
Power
Analog ground.
13
RREF
Power
PLL voltage reference. Current source for 2.4k (1%) resistor
connected to AVSS.
15
AVDD25
Power
Analog 2.5V supply.
4.2
Pin Overview (continued)
Pin
Number
Pin Name
Pin
Direction
Pin Type
Pin Description
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