FTLX1672M3BNL Product Specification

 Finisar Corporation - September 2015

Rev. C1

Page 2

I.

Pin Descriptions

Pin

Symbol

Name/Description

Ref.

1

Transmitter Ground

1

2

Transmitter Fault

2

3

Transmitter Disable. Laser output disabled on high or open.

3

4

SDA

2-wire Serial Interface Data Line

2

5

SCL

2-wire Serial Interface Clock Line

2

6

MOD_ABS

Module Absent. Grounded within the module

2

7

RS0

Rate Select 0.

4

8

RX_LOS

Loss of Signal indication. Logic 0 indicates normal operation.

5

9

RS1

Rate Select 1.

4

10

Receiver Ground

1

11

Receiver Ground

1

12

RD-

Receiver Inverted DATA out. AC Coupled.

13

RD+

Receiver Non-inverted DATA out. AC Coupled.

14

Receiver Ground

1

15

Receiver Power Supply

6

16

Transmitter Power Supply

6

17

Transmitter Ground

1

18

TD+

Transmitter Non-Inverted DATA in. AC Coupled.

19

TD-

Transmitter Inverted DATA in. AC Coupled.

20

Transmitter Ground

1

Notes:

1.

Circuit ground is internally isolated from chassis ground.

2.

T

FAULT

is an open collector/drain output, which should be pulled up with a 4.7k – 10k Ohms resistor on

the host board if intended for use. Pull up voltage should be between 2.0V to Vcc + 0.3V. A high

output indicates a transmitter fault caused by either the TX bias current or the TX output power

exceeding the preset alarm thresholds. A low output indicates normal operation. In the low state, the

output is pulled to <0.8V.

3.

4.

Internally pulled down per SFF-8431 Rev 4.1. See Sec. X of this datasheet for the logic table to use for

the internal CDRs locking modes.

5.

LOS is open collector output. Should be pulled up with 4.7k – 10k

 on host board to a voltage

between 2.0V and 3.6V. Logic 0 indicates normal operation; logic 1 indicates loss of signal.

6.

Internally connected

Figure 1. Diagram of Host Board Connector Block Pin Numbers and Names.

VeeT

VeeT

VeeR

VeeR

TD-

TD+

RD+

RD-

VccT

VccR

VeeT

VeeR

TX_Fault

SDA

SCL

MOD_ABS

RS0

RX_LOS

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

Towards

ASIC

Towards

Bezel

TX_Disable

RS1