®

MPC104

10

quired to avoid synchronization by large negative output

glitches in subsequent equipment.

The SEL-to-channel-ON time is typically 25ns and always

shorter than the typical SEL-to-channel-OFF time of 250ns.

In the worst case, an ON/OFF margin of 150ns ensures safe

switching even for timing spreads in the digital control

latches. The short interchannel switching time of 300ns

allows channel change during the vertical blanking time,

even in high-resolution graphic or broadcast systems. As

shown in the typical performance curves, the signal enve-

lope during transition from one channel to another rises and

falls symmetrically and shows less overshooting and DC

settling effects.

Power consumption is a serious problem when designing

large crosspoint fields with high component density. Most of

the buffer amplifiers are in the off-state. One important

design goal was to attain low off-state quiescent current

when no channel is selected. The low supply current of

±120µA when no channel is selected and ±4.6mA when one

channel is selected, as well as the reduced

±5V supply

voltage, conserves power, simplifies the power supply de-

sign, and results in cooler, more reliable operation.

CIRCUIT LAYOUT

The high-frequency performance of the MPC104 can be

greatly affected by the physical layout of the circuit. The

following tips are offered as suggestions, not as absolutes.

Oscillations, ringing, poor bandwidth and settling, higher

crosstalk, and peaking are all typical problems which plague

high-speed components when they are used incorrectly.

• Bypass power supplies very close to the device pins. Use

tantalum chip capacitors (approximately 2.2

µF), a parallel

470pF ceramic chip capacitor may be added if desired.

Surface-mount types are recommended due to their low

lead inductance.

• PC board traces for signal and power lines should be wide

to reduce impedance or inductance.

• Make short and low inductance traces. The entire physical

circuit should be as small as possible.

• Use a low-impedance ground plane on the component side

to ensure that low-impedance ground is available through-

out the layout. Grounded traces between the input traces

are essential to achieve high interchannel crosstalk rejec-

tion.

• Do not extend the ground plane under high-impedance

nodes sensitive to stray capacitances, such as the buffer’s

input terminals.

• Sockets are not recommended, because they add signifi-

cant inductance and parasitic capacitance. If sockets must

be used, consider using zero-profile solderless sockets.

• Use low-inductance and surface-mounted components.

Circuits using all surface mount components with the

MPC104 will offer the best AC-performance.

• A resistor (100

Ω to 150Ω) in series with the input of the

buffers may help to reduce peaking. Place the resistor as

close as possible to the pin.

• Plug-in prototype boards and wire-wrap boards will not

function well. A clean layout using RF techniques is

essential—there are no shortcuts.

FIGURE 2. Simplified Circuit Diagram.

IN

2

+V

V

OUT

(4)

DB2

(6)

–V

(3)

(7)

(5)

SEL

2

DB1

(8)

(1)

(2)

IN

1

GND

SEL

1