CS8952T datasheet(63/86 Pages) CIRRUS

63 / 86 page

DS206TPP2

CS8952T

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

CIRRUS LOGIC ADVANCED PRODUCT DATABOOK

DESIGN CONSIDERATIONS

The CS8952T is a mixed-signal device containing

the high-speed digital and analog circuits required

to implement Fast Ethernet communication. It is

important the designer adhere to the following

guidelines and recommendations for proper and re-

liable operation of the CS8952T. These guidelines

will also benefit the design with good EMC perfor-

mance.

Twisted Pair Interface

The recommended connection of the twisted-pair

interface is shown if Figure 6. The unused cable

pairs are terminated to increase the common-mode

performance. Common-mode performance is also

improved by connecting the center taps of the RX

and TX input circuits to the DC-isolated ground

plane. The 0.01 µF capacitor C1 must provide 2KV

(1,500 Vrms for 60 seconds) of isolation to meet

802.3 requirements. If a shielded RJ45 connector is

used (recommended), the shield should be connect-

ed to chassis ground.

Internal Voltage Reference

A 4.99 k

Ω 1% biasing resistor must be connected

between the CS8952T RES pin and ground. This

resistor biases the internal analog circuits of the

CS8952T and should be placed as close as possible

to RES pin. Connect the other end of this resistor

directly to the ground plane. Connect the adjacent

CS8952T ground pins (pins 85 and 87) to the

grounded end of the resistor forming a “shield”

around the RES connection.

Clocking Schemes

The CS8952T may be clocked using one of three

possible schemes: using a 25 MHz crystal and the

49.9

Ω

0.1µF

CS8952

TX+

TX-

RX+

RX-

RJ-45

SHLD

TG22-3506

49.9

Ω

0.1µF

Ω

0.01µF

2KV

Ω

Figure 6. Recommended Connection of Twisted-Pair Ports (Network Interface Card)

4.99K

Ω

VSS

RES

VSS

CS8952

Via to

Ground

Plane

Figure 7. Biasing Resistor Connection and Layout

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