HT82K96E datasheet(12/46 Pages) HOLTEK

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HT82K96E

Rev. 1.70

April 22, 2004

Once the internal WDT oscillator (RC oscillator with a

period of 31

ms/5V normally) is selected, it is first divided

by 256 (8-stage) to get the nominal time-out period of

8ms/5V. This time-out period may vary with tempera-

tures, VDD and process variations. By invoking the

WDT prescaler, longer time-out periods can be realized.

Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS)

can give different time-out periods. If WS2, WS1, and WS0

are all equal to 1, the division ratio is up to 1:128, and the

maximum time-out period is 1s/5V. If the WDT oscillator is

disabled, the WDT clock may still come from the instruc-

tion clock and operates in the same manner except that

in the HALT state the WDT may stop counting and lose

its protecting purpose. In this situation the logic can only

be restarted by external logic. The high nibble and bit 3

of the WDTS are reserved for user

¢s defined flags, which

can only be set to

²10000² (WDTS.7~WDTS.3).

If the device operates in a noisy environment, using the

on-chip 32kHz RC oscillator (WDT OSC) is strongly rec-

ommended, since the HALT will stop the system clock.

WS2

WS1

WS0

Division Ratio

000

1:1

001

1:2

010

1:4

011

1:8

1:16

1:32

1:64

1:128

WDTS Register

The WDT overflow under normal operation will initialize

²chip reset² and set the status bit ²TO². But in the HALT

mode, the overflow will initialize a

²warm reset² and only

the PC and SP are reset to zero. To clear the contents of

WDT (including the WDT prescaler), three methods are

adopted; external reset (a low level to RES), software in-

struction and a

²HALT² instruction. The software instruc-

tion include

²CLR WDT² and the other set -²CLR

WDT1

² and ²CLR WDT2². Of these two types of instruc-

tion, only one can be active depending on the ROM

code option

-²CLR WDT times selection option².Ifthe

²CLR WDT² is selected (i.e. CLRWDT times equal one),

any execution of the

²CLR WDT² instruction will clear

the WDT. In the case that

²CLR WDT² and ²CLR WDT²

are chosen (i.e. CLRWDT times equal two), these two

instructions must be executed to clear the WDT; other-

wise, the WDT may reset the chip as a result of time-out.

The time-out periods defined in WDTS can used as

²wake-up period² in the Mouse Hardware wake-up func-

tion. Please reference to Mouse Hardware Wake-up

function description.

Power Down Operation

- HALT

The HALT mode is initialized by the

²HALT² instruction

and results in the following...

· The system oscillator will be turned off but the WDT

oscillator remains running (if the WDT oscillator is se-

lected).

· The contents of the on chip RAM and registers remain

unchanged.

· WDT and WDT prescaler will be cleared and re-

counted again (if the WDT clock is from the WDT os-

cillator).

· All of the I/O ports maintain their original status.

· The PDF flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialization and the WDT overflow per-

forms a

²warm reset². After the TO and PDF flags are

examined, the reason for chip reset can be determined.

The PDF flag is cleared by system power-up or execut-

ing the

²CLR WDT² instruction and is set when execut-

ing the

²HALT² instruction. The TO flag is set if the WDT

time-out occurs, and causes a wake-up that only resets

the PC and SP; the others remain in their original status.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake up the

device by mask option. Awakening from an I/O port stim-

ulus, the program will resume execution of the next in-

struction. If it awakens from an interrupt, two sequence

may occur. If the related interrupt is disabled or the inter-

rupt is enabled but the stack is full, the program will re-

sume execution at the next instruction. If the interrupt is

enabled and the stack is not full, the regular interrupt re-

sponse takes place. If an interrupt request flag is set to

²1² before entering the HALT mode, the wake-up func-

tion of the related interrupt will be disabled. Once a

wake-up event occurs, it takes 1024 tSYS (system clock

period) to resume normal operation. In other words, a

dummy period will be inserted after a wake-up. If the

wake-up results from an interrupt acknowledge signal,

the actual interrupt subroutine execution will be delayed

by one or more cycles. If the wake-up results in the next

instruction execution, this will be executed immediately

after the dummy period is finished.

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

Reset

There are three ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

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