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GS8342T08 データシート(PDF) 29 Page - GSI Technology

部品番号 GS8342T08
部品情報  36Mb SigmaDDR-IITM Burst of 2 SRAM
PDF  35 Pages
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メーカー  GSI [GSI Technology]
ホームページ  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8342T08 データシート(HTML) 29 Page - GSI Technology

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GS8342T08/09/18/36BD-400/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 6/2012
29/35
© 2011, GSI Technology
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
Test Port Input Low Voltage
VILJ
–
0.3
0.3 * VDD
V
1
Test Port Input High Voltage
VIHJ
0.7 * VDD
VDD +0.3
V
1
TMS, TCK and TDI Input Leakage Current
IINHJ
–
300
1
uA
2
TMS, TCK and TDI Input Leakage Current
IINLJ
–
1
100
uA
3
TDO Output Leakage Current
IOLJ
–
1
1
uA
4
Test Port Output High Voltage
VOHJ
VDD – 0.2
—
V
5, 6
Test Port Output Low Voltage
VOLJ
—
0.2
V
5, 7
Test Port Output CMOS High
VOHJC
VDD – 0.1
—
V
5, 8
Test Port Output CMOS Low
VOLJC
—
0.1
V
5, 9
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < VDDn +1 V not to exceed V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V
≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDD supply.
6. IOHJ = –2 mA
7. IOLJ = + 2 mA
8. IOHJC = –100 uA
9. IOLJC = +100 uA
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDD/2
Output reference level
VDD/2
TDO
VDD/2
50
Ω
30pF*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance



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