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VCNL4100 データシート(PDF) 14 Page - Vishay Siliconix |
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VCNL4100 データシート(HTML) 14 Page - Vishay Siliconix |
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14 / 17 page ![]() VCNL4100 www.vishay.com Vishay Semiconductors Rev. 1.2, 30-Aug-16 14 Document Number: 84319 For technical questions, contact: sensorstechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 LAYOUT NOTICE AND REFERENCE CIRCUIT Circuit Layout Reference Fig. 13 - Suggested VCNL4100 Layout APPLICATION CIRCUIT BLOCK REFERENCE Fig. 14 - VCNL4100 Application Circuit Notes •VDD range: 2.5 V to 3.6 V and VIRED is recommended 5.0 V • Power path of VDD and VIRED should be independent layout •The RLED resistor value is reference for test stage, it should be adjusted again for the product usage basing on the power and the lens final design. RECOMMENDED STORAGE AND REBAKING CONDITIONS PARAMETER CONDITIONS MIN. MAX. UNIT Storage temperature 5 50 °C Relative humidity - 60 % Open time - 168 h Total time From the date code on the aluminized envelope (unopened) - 12 months Rebaking Tape and reel: 60 °C - 22 h Tube: 60 °C - 22 h V DD INT INT SCLK VCNL4100 LED CATHODE 10 9 3 2 1 0.1 μF GND SCK SDA 8 V IRED 2.2 μF 2.2 k Ω V pull up V DD PMOS S G D 2.7 Ω R LED LED+ LED- 6 5 2.2 k Ω 20 k Ω MCU SCLK SDAT 8.2 k Ω INT |
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