DS3134 datasheet(41/203 Pages) DALLAS

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DS3134

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Bits 7 to 11 / BERT Port Select Bits 0 to 4 (BPS0 to BPS4). These 5 bits select which port has the

dedicated resources of the BERT.

00000 = Port 0

01000 = Port 8

10000 = Port 0 (hi speed)

11000 = n/a

00001 = Port 1

01001 = Port 9

10001 = Port 1 (hi speed)

11001 = n/a

00010 = Port 2

01010 = Port 10

10010 = n/a

11010 = n/a

00011 = Port 3

01011 = Port 11

10011 = n/a

11011 = n/a

00100 = Port 4

01100 = Port 12

10100 = n/a

11100 = n/a

00101 = Port 5

01101 = Port 13

10101 = n/a

11101 = n/a

00110 = Port 6

01110 = Port 14

10110 = n/a

11110 = n/a

00111 = Port 7

01111 = Port 15

10111 = n/a

11111 = n/a

Bit 12 / Receive FIFO Priority Control Bit 0 (RFPC0).

Bit 13 / Receive FIFO Priority Control Bit 1 (RFPC1).

These 2 bits select the algorithm the FIFO will use to determine which HDLC Channel gets the highest

priority to the DMA to transfer data from the FIFO to the PCI Bus. In the priority decoded scheme, the

lower the HDLC channel numbers, the higher the priority.

00 = all HDLC channels are serviced Round Robin

01 = HDLC Channels 1 & 2 are Priority Decoded; other HDLC Channels are Round Robin

10 = HDLC Channels 1 to 16 are Priority Decoded; other HDLC Channels are Round Robin

11 = HDLC Channels 1 to 64 are Priority Decoded; other HDLC Channels are Round Robin

Bit 14 / Transmit FIFO Priority Control Bit 0 (TFPC0).

Bit 15 / Transmit FIFO Priority Control Bit 1 (TFPC1).

These 2 bits select the algorithm the FIFO will use to determine which HDLC Channel gets the highest

priority to the DMA to transfer data from the PCI Bus to the FIFO. In the priority decoded scheme, the

lower the HDLC channel numbers, the higher the priority.

00 = all HDLC channels are serviced Round Robin

01 = HDLC Channels 1 & 2 are Priority Decoded; other HDLC Channels are Round Robin

10 = HDLC Channels 1 to 16 are Priority Decoded; other HDLC Channels are Round Robin

11 = HDLC Channels 1 to 64 are Priority Decoded; other HDLC Channels are Round Robin

4.3 STATUS & INTERRUPT

4.3.1 Status & Interrupt General Description of Operation

There are three status register in the device, Status Master (SM), Status for the Receive V54 Loopback

Detector (SV54), and Status for DMA (SDMA). All three registers report events in real time as they

occur by setting a bit within the register to a one. All bits that have been set within the register are cleared

when the register is read and the bit will not be set again until the event has occurred again. Each bit has

the ability to generate an interrupt at the PCI Bus via the PINTA* output signal pin and if the Local Bus is

in the Configuration Mode, then an interrupt will also be created at the LINT* output signal pin. Each

status register has an associated Interrupt Mask Register, which can allow/deny interrupts from being

generated on a bit-by-bit basis. All status remains active even if the associated Interrupt is disabled.

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