MCP9902 datasheet(14/50 Pages) MICROCHIP

14 / 50 page

MCP9902/3/4

DS20005382C-page 14

 2015-2016 Microchip Technology Inc.

4.13.1

HIGH LIMIT REGISTER

The High Limit Status register contains the status bits

that are set when a temperature channel high limit is

exceeded. If any of these bits are set, then the HIGH

status bit in the Status register is set. Reading from the

High Limit Status register will clear all bits. Reading

from the register will also clear the HIGH status bit in

the Status register.

The ALERT/THERM2 pin will be set if the pro-

grammed number of consecutive alert counts have

been met and any of these status bits are set.

The status bits will remain set until read unless the

ALERT/THERM2 pin is configured as a comparator

output (see Section 4.6.2 “ALERT/THERM2 Pin In

THERM Mode”

4.13.2

LOW LIMIT REGISTER

The Low Limit Status register contains the status bits

that are set when a temperature channel drops below

the low limit. If any of these bits are set, then the LOW

status bit in the Status register is set. Reading from the

Low Limit Status register will clear all bits.

The ALERT/THERM2 pin will be set if the pro-

grammed number of consecutive alert counts have

been met and any of these status bits are set.

The status bits will remain set until read unless the

ALERT/THERM2 pin is configured as a comparator

output (see Section 4.6.2 “ALERT/THERM2 Pin In

THERM Mode”

4.13.3

THERM LIMIT REGISTER

The Therm Limit registers are used to determine

whether a critical thermal event has occurred. If the

measured temperature exceeds the Therm Limit, the

THERM pin is asserted. The limit setting must match

the chosen data format of the temperature reading

registers.

Unlike the ALERT/THERM2 pin, the THERM pin

cannot be masked. Additionally, the THERM pin will be

released once the temperature drops below the

corresponding threshold minus the Therm Hysteresis.

4.13.4

CHANNEL MASKING

The Channel Mask register (Register 5-20) controls

individual channel masking. When a channel is

masked, the ALERT/THERM2 pin will not be asserted

when the masked channel reads a diode fault or out of

limit error. The channel mask does not mask the

THERM pin.

4.14

Digital Filter

To reduce the effect of noise and temperature spikes on

the reported temperature, the External Diode channel

uses a programmable digital filter. This filter can be con-

figured as Level 1, Level 2, or Disabled (default). The

typical filter performance is shown in Figure 4-2 and

Figure 4-3. The Filter Configuration register controls the

digital filter on the External Diode 1 channel.

Note 1:

Filtering Level 1 corresponds to 4x

attenuation of a temperature spike.

Filtering Level 2 corresponds to 8x

attenuation of a temperature spike.

FIGURE 4-2:

Temperature Filter Step

Response.

FIGURE 4-3:

Temperature Filter Impulse

Response.

TABLE 4-6:

FILTER SETTINGS

FILTER<1:0>

Averaging

Disabled (default)

Level 1

Level 2

02468

Samples

Disable

Level 2

Level 1

02468

Samples

Disabled

Level 1

Level 2

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