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TSC2000IPW データシート(PDF) 4 Page - Texas Instruments

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部品番号 TSC2000IPW
部品情報  PDA ANALOG INTERFACE CIRCUIT
PDF  38 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

TSC2000IPW データシート(HTML) 4 Page - Texas Instruments

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TSC2000
SBAS257
TIMING DIAGRAM
All specifications typical at –40
°C to +85°C, +V
DD = +2.7V.
t
td
t
Lag
t
dis
t
Lead
t
sck
t
wsck
t
wsck
t
hi
t
su
t
ho
t
a
t
v
t
r
t
f
SS
SCLK
MSB OUT
MSB IN
LSB IN
LSB OUT
BIT 6 ... 1
BIT 6 ... 1
MISO
MOSI
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Period
tsck
30
ns
Enable Lead Time
tLead
15
ns
Enable Lag Time
tLag
15
ns
Sequential Transfer Delay
ttd
30
ns
Data Setup Time
tsu
10
ns
Data Hold Time (inputs)
thi
10
ns
Data Hold Time (outputs)
tho
0ns
Slave Access Time
ta
15
ns
Slave DOUT Disable Time
tdis
15
ns
DataValid
tv
10
ns
Rise Time
tr
30
ns
Fall Time
tf
30
ns
TIMING CHARACTERISTICS(1)(2)
At –40
°C to +85°C, +V
DD = +2.7V, VREF = +2.5V, unless otherwise noted.
TSC2000
NOTES: (1) All input signals are specified with tr = tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagram below.



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