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ST7MC1 データシート(PDF) 78 Page - STMicroelectronics |
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ST7MC1 データシート(HTML) 78 Page - STMicroelectronics |
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78 / 308 page ![]() ST7MC1/ST7MC2 78/308 16-BIT TIMER (Cont’d) Figure 45. Counter Timing Diagram, internal clock divided by 2 Figure 46. Counter Timing Diagram, internal clock divided by 4 Figure 47. Counter Timing Diagram, internal clock divided by 8 Note: The Device is in reset state when the internal reset signal is high, when it is low the Device is run- ning. CPU CLOCK FFFD FFFE FFFF 0000 0001 0002 0003 INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 1 |
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