ST7MC1 datasheet(290/308 Pages) STMICROELECTRONICS

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14 ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in ROM

versions and in user programmable versions

(FLASH) as well as in factory coded versions

(FASTROM). ST7MC are ROM devices. ST7PMC

devices are Factory Advanced Service Technique

ROM (FASTROM) versions: they are programmed

FLASH devices.

ST7FMC FLASH devices are shipped to custom-

ers with a default content (FFh), while ROM/FAS-

TROM factory coded parts contain the code sup-

plied by the customer. This implies that FLASH de-

vices have to be configured by the customer using

the Option Bytes while the ROM devices are facto-

ry-configured.

14.1 FLASH OPTION BYTES

The option bytes allow the hardware configuration

of the microcontroller to be selected. They have no

address in the memory map and can be accessed

only in programming mode (for example using a

standard ST7 programming tool). The default con-

tent of the FLASH is fixed to FFh. This means that

all the options have “1” as their default value.

OPTION BYTE 0

OPT7= WDG HALT Watchdog and HALT mode

This option bit determines if a RESET is generated

when entering HALT mode while the Watchdog is

active.

0: No Reset generation when entering Halt mode

1: Reset generation when entering Halt mode

OPT6= WDG SW Hardware or software watchdog

This option bit selects the watchdog type.

0: Hardware (watchdog always enabled)

1: Software (watchdog to be enabled by software)

OPT5 = CKSEL Clock Source Selection.

0: PLL clock selected1)

1: Oscillator clock selected

Note 1: Even if PLL clock is selected, a clock signal must

always be present (refer to Figure 13. on page 27)

OPT4:3= VD[1:0] Voltage detection

These option bits enable the voltage detection

block (LVD, and AVD).

OPT2 = RSTC RESET clock cycle selection

This option bit selects the number of CPU cycles

applied during the RESET phase and when exiting

HALT mode. For resonator oscillators, it is advised

to select 4096 due to the long crystal stabilization

time.

0: Reset phase with 4096 CPU cycles

1: Reset phase with 256 CPU cycles

Note: When the PLL clock is selected (CKSEL=0),

the reset clock cycle selection is forced to 4096

CPU cycles.

OPT1= DIV2 Divider by 2

1: DIV2 divider disabled with OSCIN = 8MHz

0: DIV2 divider enabled (in order to have 8 MHz re-

quired for the PLL with OSCIN =16 Mhz))

OPT0= FMP_R Flash memory read-out protection

Readout protection, when selected provides a pro-

tection against program memory content extrac-

tion and against write access to Flash memory.

This protection is based on a read/write protection

of the memory in test modes and ICP mode. Eras-

ing the option bytes when the FMP_R option is se-

lected causes the whole user memory to be

erased first and the device can be reprogrammed.

Refer to the ST7 Flash Programming Reference

Manual and section 4.3.1 on page 21 for more de-

tails.

0: Read-out protection enabled

1: Read-out protection disabled

STATIC OPTION BYTE 0

STATIC OPTION BYTE 1

WDG

PKG

MCO

Default

value

Selected Low Voltage Detector

VD1

VD0

LVD and AVD On

LVD On and AVD Off

LVD and AVD Off

Selected Low Voltage Detector

VD1

VD0

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