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YMF724F データシート(PDF) 21 Page - YAMAHA CORPORATION |
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YMF724F データシート(HTML) 21 Page - YAMAHA CORPORATION |
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21 / 50 page  YMF724F January 14, 1999 -21- 46-47h: Subsystem ID Write Register Read / Write Default: 000Dh Access Bus Width: 16-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsystem ID Write b[15:0] ........Subsystem ID Write Register This register sets the Subsystem ID that is read from 2E-2Fh (Subsystem ID register). The default value is the DS-1 Device ID, 000Dh. IHVs must change this ID to their ID in the BIOS POST routine. In case EEPROM connects externally, this register is invalid, and do not reflect to Subsystem ID. 48-49h: DS-1 Control Register Read / Write Default: 0001h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - - - - - - - - - XRST CRST b0................CRST: AC’97 Software Reset Signal Control This bit controls the CRST# signal. “0”: Inactive (CRST#=High) “1”: Active (CRST#=Low) (default) b1................XRST: Local Device Software Reset Signal Control This bit controls the XRST# signal. “0”: Inactive (XRST#=High) (default) “1”: Active (XRST#=Low) 4A-4Bh: DS-1 Power Control Register Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 - - PSN PSL1 PSL0 DPLL1 DPLL0 DMC b0................DMC: Disable Master Clock Oscillation Setting this bit to “1” disables the oscillation of the Master Clock (24.576 MHz). “0”: Normal (default) “1”: Disable b1................DPLL0: Disable PLL0 Clock Oscillation Setting this bit to “1” disables the oscillation of PLL for the Legacy Audio function. “0”: Normal (default) “1”: Disable |
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