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AD1835AS データシート(PDF) 5 Page - Analog Devices

部品番号 AD1835AS
部品情報  2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
PDF  23 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD1835AS データシート(HTML) 5 Page - Analog Devices

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REV. PrA
PRELIMINARY TECHNICAL DATA
–5–
AD1835
Parameter
Min
Max
Unit
Comments
TDM256 MODE (Master)
tTBD
BCLK Delay
20
ns
From MCLK Rising
tFSD
FSTDM Delay
5
ns
From BCLK Rising
tTABDD
ASDATA Delay
10
ns
From BCLK Rising
tTDDS
DSDATA1 Setup
15
ns
To BCLK Falling
tTDDH
DSDATA1 Hold
15
ns
From BCLK Falling
TDM256 MODE (Slave)
fAB
BCLK Frequency
256
fS
ns
tTBCH
BCLK High
min
ns
tTBCL
BCLK Low
min
ns
tTFS
FSTDM Setup
min
ns
To BCLK Falling
tTFH
FSTDM Hold
min
ns
From BCLK Falling
tABDD
ASDATA Delay
max
ns
From BCLK Rising
tTDDS
DSDATA1 Setup
min
ns
To BCLK Falling
tTDDH
DSDATA1 Hold
min
ns
From BCLK Falling
TDM512 MODE (Master)
tABDH
BCLK Delay
40
ns
From MCLK Rising
tFSD
FSTDM Delay
5
ns
From BCLK Rising
tTABDD
ASDATA Delay
10
ns
From BCLK Rising
tTDDS
DSDATA1 Setup
15
ns
To BCLK Falling
tTDDH
DSDATA1 Hold
15
ns
From BCLK Falling
TDM512 MODE (Slave)
fAB
BCLK Frequency
512
fS
tTBCH
BCLK High
20
ns
tTBCL
BCLK Low
20
ns
tTFS
FSTDM Setup
5
ns
To BCLK Rising
tTFH
FSTDM Hold
10
ns
From BCLK Rising
tTABDD
ASDATA Delay
20
ns
From BCLK Rising
tTDDS
DSDATA1 Setup
5
ns
To BCLK Rising
tTDDH
DSDATA1 Hold
10
ns
From BCLK Rising
AUXILIARY INTERFACE
tAXDS
AAUXDATA Setup
10
ns
To AUXBCLK Rising
tAXDH
AAUXDATA Hold
10
ns
From AUXBCLK Rising
fABP
AUXBCLK Frequency
64
fS
Slave Mode
tAXBH
AUXBCLK High
15
ns
tAXBL
AUXBCLK Low
15
ns
tAXLS
AUXLRCLK Setup
10
ns
To AUXBCLK Rising
tAXLH
AUXLRCLK Hold
10
ns
From AUXBCLK Rising
Master Mode
tAUXLRCLK
AUXLRCLK Delay
5
ns
From AUXBCLK Falling
tAUXBCLK
AUXBCLK Delay
15
ns
From MCLK Rising Edge
Specifications subject to change without notice.



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