MCP3918A1-ESLASHML datasheet(33/88 Pages) MICROCHIP

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DS20005287A-page 33

MCP3918

5.3.4

DITHER SETTINGS

The modulator includes a dithering algorithm that can

be enabled through the DITHER<1:0> bits in the

CONFIG0 register. This dithering process improves

THD and SFDR (for high OSR settings), while slightly

increasing the noise floor of the ADC. For power

metering applications and applications that are

distortion-sensitive, it is recommended to keep

DITHER at maximum settings for best THD and SFDR

performance. In the case of power metering

applications, THD and SFDR are critical specifications.

Optimizing SNR (noise floor) is not problematic due to

the large averaging factor at the output of the ADC.

Therefore, even for low OSR settings, the dithering

algorithm will show a positive impact on the

performance of the application.

5.3.5

MODULATOR OUTPUT BLOCK

If the user wishes to use the modulator output of the

device, the EN_MDAT bit in the STATUSCOM register

must be set to enable.

When the EN_MDAT bit is enabled, the modulator

output is present at the MDAT0 output pin as soon as

the command is placed. Additionally, the corresponding

sinc filter is disabled in order to consume less current.

The corresponding Data Ready pulse is not present

either at the DR output pin. When the EN_MDAT bit is

cleared, the sinc filter is back to normal operation and

the MDAT0 output is high-impedance. The data ready

output pin is then placed in high-impedance regardless

of the DR_HIZ setting, so that the user can tie this pin

to an external supply or ground for lower noise

behavior.

Since the delta-sigma modulator has a five-level output

given by the state of the four comparators with

thermometer coding, its output can be represented on

four bits, each bit giving the state of the corresponding

comparator (see Table 5-3). These bits are present in

the MOD register and are updated at the DMCLK rate.

In order to output the result of the comparator on a

separate pin (MDAT0), this comparator output bit has

been arranged to be serially output at the AMCLK rate

(see Figure 5-2).

This 1-bit serial bit stream is the same that would be

produced by a 1-bit DAC modulator with a sampling

frequency of AMCLK. The modulator can either be

considered as a five-level output at DMCLK rate or a

1-bit output at AMCLK rate. These two representations

are interchangeable. The MDAT0 output can therefore

be used in any application that requires 1-bit modulator

outputs. Such applications will often integrate and filter

the 1-bit output with sinc or more complex decimation

filters computed by a MCU or a DSP.

FIGURE 5-2:

MDAT0 Serial Output with

Respect to the Modulator Output Code.

Since the Reset and Shutdown SPI commands are

asynchronous, the MDAT0 pin is resynchronized with

DMCLK after each time the part goes out of reset and

shutdown.

This means that, after a soft reset or a shutdown, the

first output of MDAT0 is always 0011 after the first

DMCLK rising edge.

The MDAT0 output pin is high-impedance if the RESET

pin is low and in 2-wire interface mode.

TABLE 5-3:

DELTA-SIGMA MODULATOR

CODING

Comp<3:0>

Code

Modulator

Output Code

MDAT Serial

Stream

1111

0111

0011

0001

-1

0001

0000

-2

0000

DMCLK

MDAT+2

MDAT+1

MDAT+0

MDAT-1

MDAT-2

COMP

AMCLK

<3>

COMP

<2>

COMP

<1>

COMP

<0>

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