© VITESSE SEMICONDUCTOR CORPORATION

Page 5

9/29/00

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC8115

STS-12/STS-3 Multi Rate

Clock and Data Recovery Unit

G52272-0, Rev. 1.1

Jitter Tolerance

Jitter Tolerance is the ability of the Clock and Data Recovery Unit to track timing variation in the received

data stream. The Bellcore and ITU specifications allow the received optical data to contain jitter. The amount

that must be tolerated is a function of the frequency of the jitter. At high frequencies the specifications do not

require the VSC8115 to tolerate large amounts, whereas at low frequencies many unit intervals (bit times) of jit-

ter have to be tolerated. Jitter tolerance is defined as the ratio of jitter on the output OC-N/STS-N signal to the

jitter applied on the input OC-N/STSN signal versus frequency. The VSC8115 is designed to tolerate this jitter

with margin over the specification limits, see Figure 2. The VSC8115 obtains and maintains lock based on the

data transition information. When there is no transition on the data stream, the recovered clock frequency will

be held to within +500ppm of the reference clock. The VSC8115 can maintain lock over 1000 bits of no switch-

ing on data stream.

Figure 2: Input Jitter Tolerance Specification

Jitter Generation

Jitter generation is defined as the jitter of the serial clock and serial data outputs while rms jitter is presented

to the serial data inputs. Maximum jitter generation is 0.01 U.I. when rms jitter of less than 14ps (OC-12) or

56ps (OC-3) is presented to the serial data inputs.

10

30

300

25K

250K

15

1.5

0.15

2.5M

150

24

2.4

0.6

Bellcore Requirement

VSC8115 Typical

Jitter Tolerance

1M