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LE25S161 データシート(PDF) 15 Page - ON Semiconductor

部品番号 LE25S161
部品情報  Serial Flash Memory
PDF  54 Pages
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LE25S161 データシート(HTML) 15 Page - ON Semiconductor

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9-1-4. SUS (bit 6)
The SUS register indicates when Erase/Program operation has been suspended. The SUS becomes "1" when the
Erase/Program operation has been suspended (WSUS: B0h). The SUS is cleared to"0" by Resume (RESM:30h) or
re-erase/program (SSE, SE, CHE, PP, PPL).
9-1-5. SRWP (bit 7)
Write Status Register protect SRWP is the bit for protecting the status registers, and its information can be rewritten.
When SRWP is "1" and the logic level of the WP pin is low, the Write Status Register (WRSR: 01h) is ignored, and status
registers BP0, BP1, BP2, TB and SRWP are protected. When the logic level of the WP pin is high, the status registers are
not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 5. SRWP Setting
Conditions".
Table 5. SRWP Setting Conditions
WP Pin
SRWP
Status Register Protect State
0
0
Unprotected
1
Protected
1
0
Unprotected
1
Unprotected



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