TABLE 3. Suggested Capacitors and Their Suppliers

Model

Size

Vendor

Phone

FAX

22µF, X7R or X5R Ceramic Capacitor for C2 (Output Filter Capacitor)

C3225X5RIA226M

1210

TDK

847-803-6100

847-803-6296

JMK325BJ226MM

1210

Taiyo-Yuden

847-925-0888

847-925-0899

ECJ4YB0J226M

1210

Panasonic

714-373-7366

714-373-7323

GRM42-2X5R226K6.3

1210

muRata

404-436-1300

404-436-3030

10µF, 6.3V, X7R or X5R Ceramic Capacitor for C1 (Input Filter Capacitor)

C2012X5R0J106M

0805

TDK

847-803-6100

847-803-6296

JMK212BJ106MG

0805

Taiyo Yuden

847-925-0888

847-925-0899

ECJ3YB0J106K

1206

Panasonic

714-373-7366

714-373-7323

GRM40X5R106K6.3

0805

muRata

404-436-1400

404-436-3030

CAPACITOR SELECTION

Use a 10µF, 6.3V, X7R or X5R ceramic input filter capacitor

and a 22uF, X7R or X5R ceramic output filter capacitor.

These provide an optimal balance between small size, cost,

reliability and performance. Do not use Y5V ceramic capaci-

tors. Table 3 lists suggested capacitors and suppliers.

A 10µF ceramic capacitor can be used for the output filter

capacitor for smaller size in applications where the worst-

case transient load step is less than 200mA. Use of a 10µF

output capacitor trades off smaller size for an increase in

output voltage ripple, and undershoot during line and load

transient response.

The input filter capacitor supplies current to the PFET switch

of the LM2612 in the first part of each cycle and reduces

voltage ripple imposed on the input power source. The out-

put filter capacitor smoothes out current flow from the induc-

tor to the load, helps maintain a steady output voltage during

transient load changes and reduces output voltage ripple.

These capacitors must be selected with sufficient capaci-

tance and sufficiently low ESR to perform these functions.

The ESR, or equivalent series resistance, of the filter capaci-

tors is a major factor in voltage ripple. The contribution from

ESR to voltage ripple is around 75-95% for most electrolytic

capacitors and considerably less for ceramic capacitors. The

remainder of the ripple is from charge storage due to capaci-

tance.

DIODE SELECTION

An optional Schottky diode (D1 in Figure 1) can be added to

increase efficiency in PFM mode and PWM mode. This may

be desired in applications where increased efficiency for

improving operational battery life takes precedence over

increased system size associated with the Schottky diode.

Typically, use of an external schottky diode increases PFM

mode efficiency from 72.7% to 85.0% (20 mA load, V

1.8V, V

Operating Characteristics.

Use a Schottky diode with a current rating higher than maxi-

mum current limit, such as an MBRM120T3 or MBRM140T3.

Use of a device rated for 30V or more reduces diode reverse

leakage in high temperature applications

MICRO SMD PACKAGE ASSEMBLY AND USE

Use of the micro SMD package requires specialized board

layout, precision mounting and careful reflow techniques, as

detailed in National Semiconductor Application Note AN-

1112. Refer to the section Surface Mount Technology (SMT)

Assembly Considerations. For best results in assembly,

alignment ordinals on the PC board should be used to

facilitate placement of the device. Since micro SMD packag-

ing is a new technology, all layouts and assembly means

must be thoroughly tested prior to production. In particular,

proper placement, solder reflow and resistance to thermal

cycling must be verified.

The 10-Bump package used for the LM2612 has 300micron

solder balls and requires 10.82mil (0.275mm) pads for

mounting on the circuit board. The trace to each pad should

enter the pad with a 90˚ entry angle to prevent debris from

being caught in deep corners. Initially, the trace to each pad

should be 6 mil wide, for a section 6 mil long or longer, as a

thermal relief. Then each trace should neck up to its optimal

width over a span of 11 mils or more, so that the taper

extends beyond the edge of the package. The important

criterion is symmetry. This ensures the solder bumps on the

LM2612 re-flow evenly and that the device solders level to

the board. In particular, special attention must be paid to the

pads for bumps A3, B3, C3, D3 and A2. Because PVIN and

PGND are typically connected to large copper planes, inad-

equate thermal reliefs can result in late or inadequate reflow

of these bumps.

The pad style used with micro SMD package must be the

NSMD (non-solder mask defined) type. This means that the

solder-mask opening is larger than the pad size or 14.7mils

for the LM2612. This prevents a lip that otherwise forms if

the solder-mask and pad overlap. This lip can hold the

device off the surface of the board and interfere with mount-

ing. See Applications Note AN-1112 for specific instructions.

BOARD LAYOUT CONSIDERATIONS

PC board layout is an important part of DC-DC converter

design. Poor board layout can disrupt the performance of a

DC-DC converter and surrounding circuitry by contributing to

EMI, ground bounce, and resistive voltage loss in the traces.

These can send erroneous signals to the DC-DC converter

IC, resulting in poor regulation or instability. Poor layout can

also result in reflow problems leading to poor solder joints

between the micro SMD package and board pads. Poor

solder joints can result in erratic or degraded performance.

Good layout for the LM2612 can be implemented by follow-

ing a few simple design rules:

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